| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat64InstrInfo.td | 171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT. 175 def : PatFPSetcc<SETOLE, FCMP_CLE_D, FPR64>; 188 defm : PatFPBrcond<SETOLE, FCMP_CLE_D, FPR64>; 202 def : PatStrictFsetccs<SETOLE, FCMP_SLE_D, FPR64>; 221 def : PatFPSelectcc<SETOLE, FCMP_CLE_D, FSEL_xD, FPR64>;
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| H A D | LoongArchFloat32InstrInfo.td | 195 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT. 199 def : PatFPSetcc<SETOLE, FCMP_CLE_S, FPR32>; 220 defm : PatFPBrcond<SETOLE, FCMP_CLE_S, FPR32>; 237 def : PatStrictFsetccs<SETOLE, FCMP_SLE_S, FPR32>; 260 def : PatFPSelectcc<SETOLE, FCMP_CLE_S, FSEL_xS, FPR32>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZfa.td | 265 def: PatSetCC<FPR32, strict_fsetcc, SETOLE, FLEQ_S, f32>; 290 def: PatSetCC<FPR64, strict_fsetcc, SETOLE, FLEQ_D, f64>; 320 def: PatSetCC<FPR16, strict_fsetcc, SETOLE, FLEQ_H, f16>;
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| H A D | RISCVInstrInfoD.td | 418 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_D, Ext>; 438 def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D, f64>; 458 def : PatSetCC<FPR64INX, any_fsetccs, SETOLE, FLE_D_INX, f64>; 478 def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLE, FLE_D_IN32X, f64>;
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| H A D | RISCVInstrInfoZfh.td | 397 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_H, Ext>; 434 defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_H, Ext>;
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| H A D | RISCVInstrInfoF.td | 672 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_S, Ext>; 709 defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_S, Ext>;
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| H A D | RISCVInstrInfoVSDPatterns.td | 1388 defm : VPatFPSetCCSDNode_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF2.td | 384 defm : BRCond_Bin_SWAP_F2<SETOLE, "f2FCMPHS", BT32, BF32, MVC32>; 408 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLE)), bb:$imm16), 410 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOLE)), 412 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLE)), FPR32Op:$rx, FPR32Op:$false),
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| H A D | CSKYInstrInfoF1.td | 364 defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, BF32, MVC32>; 384 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)), bb:$imm16), 386 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)),
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 206 case FCmpInst::FCMP_OLE: return ISD::SETOLE; in getFCmpCondCode() 226 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1692 SETOLE, // 0 1 0 1 True if ordered and less than or equal enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.h | 116 case ISD::SETOLE: in fpCondCode2Fcc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrFloat.td | 88 defm LE : ComparisonFP<SETOLE, "le ", 0x5f, 0x65>;
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| H A D | WebAssemblyInstrSIMD.td | 799 defm LE : SIMDConditionFP<"le", SETOLE, 69>;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 527 case ISD::SETOLE: return "setole"; in getOperationName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructions.td | 353 def COND_OLE : PatFrags<(ops), [(OtherVT SETOLE), (OtherVT SETLE)]>;
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| H A D | SIWholeQuadMode.cpp | 865 case ISD::SETOLE: in lowerKillF32()
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| H A D | R600ISelLowering.cpp | 87 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4234 case ISD::SETOLE: in SelectCC() 4261 case ISD::SETOLE: in SelectCC() 4290 case ISD::SETOLE: in getPredicateForSetCC() 4343 case ISD::SETOLE: in getCRIdxForSetCC() 4366 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; in getVCmpInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 844 case ISD::SETOLE: in IntCondCCodeToICC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1791 case ISD::SETOLE: in TranslateM68kCC() 1814 case ISD::SETOLE: // flipped in TranslateM68kCC()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 912 def SETOLE : CondCode<"FCMP_OLE">; 1580 (setcc node:$lhs, node:$rhs, SETOLE)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 865 case ISD::SETOLE: in getFPBranchKind()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 384 case ISD::SETOLE: in getPTXCmpMode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 351 setCondCodeAction(ISD::SETOLE, MVT::v64f16, Expand); in initializeHVXLowering() 366 setCondCodeAction(ISD::SETOLE, MVT::v32f32, Expand); in initializeHVXLowering()
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