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Searched refs:SETOEQ (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td190 def : PatFPSetcc<SETOEQ, FCMP_CEQ_S, FPR32>;
212 defm : PatFPBrcond<SETOEQ, FCMP_CEQ_S, FPR32>;
229 def : PatStrictFsetccs<SETOEQ, FCMP_SEQ_S, FPR32>;
252 def : PatFPSelectcc<SETOEQ, FCMP_CEQ_S, FSEL_xS, FPR32>;
H A DLoongArchFloat64InstrInfo.td170 def : PatFPSetcc<SETOEQ, FCMP_CEQ_D, FPR64>;
184 defm : PatFPBrcond<SETOEQ, FCMP_CEQ_D, FPR64>;
198 def : PatStrictFsetccs<SETOEQ, FCMP_SEQ_D, FPR64>;
217 def : PatFPSelectcc<SETOEQ, FCMP_CEQ_D, FSEL_xD, FPR64>;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1577 SETOEQ, // 0 0 0 1 True if ordered and equal enumerator
1626 return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE; in isFPEqualitySetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td403 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_D, Ext>;
415 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),
421 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)),
435 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETOEQ)),
441 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETOEQ)),
455 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)),
461 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETOEQ)),
H A DRISCVInstrInfoZfh.td359 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_H, Ext>;
371 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETOEQ)),
377 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETOEQ)),
386 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETOEQ)),
392 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETOEQ)),
H A DRISCVInstrInfoF.td610 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_S, Ext>;
622 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ)),
628 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ)),
637 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETOEQ)),
643 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETOEQ)),
H A DRISCVInstrInfoVSDPatterns.td1375 defm : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
H A DRISCVISelLowering.cpp5878 SDValue XIsNonNan = DAG.getSetCC(DL, XLenVT, X, X, ISD::SETOEQ); in lowerFMAXIMUM_FMINIMUM()
5884 SDValue YIsNonNan = DAG.getSetCC(DL, XLenVT, Y, Y, ISD::SETOEQ); in lowerFMAXIMUM_FMINIMUM()
5918 {X, X, DAG.getCondCode(ISD::SETOEQ), in lowerFMAXIMUM_FMINIMUM()
5927 {Y, Y, DAG.getCondCode(ISD::SETOEQ), in lowerFMAXIMUM_FMINIMUM()
11030 if (CCVal == ISD::SETEQ || CCVal == ISD::SETOEQ) { in lowerVectorStrictFSetcc()
11046 SDValue OEQCCVal = DAG.getCondCode(ISD::SETOEQ); in lowerVectorStrictFSetcc()
11073 {Chain, Op1, Op1, DAG.getCondCode(ISD::SETOEQ), DAG.getUNDEF(MaskVT), in lowerVectorStrictFSetcc()
11077 {Chain, Op2, Op2, DAG.getCondCode(ISD::SETOEQ), DAG.getUNDEF(MaskVT), in lowerVectorStrictFSetcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td378 defm : BRCond_Bin_F2<SETOEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
464 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOEQ)), bb:$imm16),
466 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOEQ)),
468 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOEQ)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td358 defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, BT32, MVCV32>;
396 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)), bb:$imm16),
398 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)),
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp202 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; in getFCmpCondCode()
223 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td84 defm EQ : ComparisonFP<SETOEQ, "eq ", 0x5b, 0x61>;
H A DWebAssemblyInstrSIMD.td754 defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp501 case ISD::SETOEQ: return "setoeq"; in getOperationName()
H A DTargetLowering.cpp320 case ISD::SETOEQ: in softenSetCCOperands()
5216 if ((Cond == ISD::SETOEQ || Cond == ISD::SETUEQ) && CFP->isInfinity()) { in SimplifySetCC()
5236 case ISD::SETOEQ: NewCond = IsNegInf ? ISD::SETOLE : ISD::SETOGE; break; in SimplifySetCC()
8597 ISD::CondCode OrderedCmpOpcode = IsInverted ? ISD::SETUNE : ISD::SETOEQ; in expandIS_FPCLASS()
8621 isCondCodeLegalOrCustom(IsInverted ? ISD::SETUNE : ISD::SETOEQ, in expandIS_FPCLASS()
8629 IsInverted ? ISD::SETUNE : ISD::SETOEQ); in expandIS_FPCLASS()
11589 assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && in LegalizeSetCCCondCode()
11594 assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && in LegalizeSetCCCondCode()
11596 CC1 = ISD::SETOEQ; in LegalizeSetCCCondCode()
11597 CC2 = ISD::SETOEQ; in LegalizeSetCCCondCode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td348 def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;
H A DSIWholeQuadMode.cpp839 case ISD::SETOEQ: in lowerKillF32()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp858 case ISD::SETOEQ: in IntCondCCodeToICC()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4295 case ISD::SETOEQ: in getPredicateForSetCC()
4332 case ISD::SETOEQ: in getCRIdxForSetCC()
4376 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break; in getVCmpInst()
4384 case ISD::SETOEQ: in getVCmpInst()
H A DPPCInstrInfo.td3933 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),
3977 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)),
4004 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)),
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td849 def SETOEQ : CondCode<"FCMP_OEQ">;
1483 (setcc node:$lhs, node:$rhs, SETOEQ)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td2044 defm FCMEQ_PPzZZ : sve_fp_3op_p_pd_cc<0b010, "fcmeq", SETOEQ, SETEQ, SETOEQ, SETEQ>;
2054 defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq", SETOEQ, SETEQ, SETOEQ, SETEQ>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td126 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
127 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1827 case ISD::SETOEQ: in TranslateM68kCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp580 case ISD::SETOEQ: in getPTXCmpMode()

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