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Searched refs:SETNE (Results 1 – 25 of 69) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h97 return selectSETCC(N, ISD::SETNE, Val); in selectSETNE()
175 case ISD::SETNE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td1025 defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>;
1033 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSNE", SETNE, SETNE>;
1043 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSNE", SETNE, SETNE>;
1377 defm : VPatFPSetCCSDNode_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">;
H A DRISCVISelLowering.cpp440 ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; in RISCVTargetLowering()
2979 {Src, Src, DAG.getCondCode(ISD::SETNE), in lowerFP_TO_INT_SAT()
4052 return DAG.getSetCC(DL, VT, WideVec, VecZero, ISD::SETNE); in lowerBUILD_VECTOR()
5103 ISD::SETNE); in lowerVECTOR_SHUFFLE()
5541 {Source, AllZero, DAG.getCondCode(ISD::SETNE), in lowerVPCttzElements()
5738 ISD::SETNE); in lowerSADDO_SSUBO()
5754 ISD::SETNE); in lowerSMULO()
5810 ISD::SETNE); in LowerIS_FPCLASS()
5846 {AND, SplatZero, DAG.getCondCode(ISD::SETNE), in LowerIS_FPCLASS()
5854 ISD::CondCode::SETNE); in LowerIS_FPCLASS()
[all...]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1599 SETNE, // 1 X 1 1 0 True if not equal enumerator
1620 return Code == SETEQ || Code == SETNE; in isIntEqualitySetCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp224 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
236 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
254 case ISD::SETNE: in getICmpCondCode()
H A DTargetLoweringBase.cpp584 CmpLibcallCCs[RTLIB::UNE_F32] = ISD::SETNE; in initCmpLibcallCCs()
585 CmpLibcallCCs[RTLIB::UNE_F64] = ISD::SETNE; in initCmpLibcallCCs()
586 CmpLibcallCCs[RTLIB::UNE_F128] = ISD::SETNE; in initCmpLibcallCCs()
587 CmpLibcallCCs[RTLIB::UNE_PPCF128] = ISD::SETNE; in initCmpLibcallCCs()
604 CmpLibcallCCs[RTLIB::UO_F32] = ISD::SETNE; in initCmpLibcallCCs()
605 CmpLibcallCCs[RTLIB::UO_F64] = ISD::SETNE; in initCmpLibcallCCs()
606 CmpLibcallCCs[RTLIB::UO_F128] = ISD::SETNE; in initCmpLibcallCCs()
607 CmpLibcallCCs[RTLIB::UO_PPCF128] = ISD::SETNE; in initCmpLibcallCCs()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp325 case ISD::SETNE: in softenSetCCOperands()
3985 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithAnd()
3990 if (Cond == ISD::SETNE && isNullConstant(N1) && in foldSetCCWithAnd()
4111 NewCond = ISD::CondCode::SETNE; in optimizeSetCCOfSignedTruncationCheck()
4115 NewCond = ISD::CondCode::SETNE; in optimizeSetCCOfSignedTruncationCheck()
4168 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4241 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"); in foldSetCCWithBinOp()
4312 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4317 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) { in simplifySetCCWithCTPOP()
4350 if (Cond != ISD::SETEQ && Cond != ISD::SETNE) in foldSetCCWithRotate()
[all …]
H A DLegalizeIntegerTypes.cpp1298 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
1724 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
1824 ISD::SETNE); in PromoteIntRes_XMULO()
1829 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
3485 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_ADDSUB()
3623 DAG.getConstant(0, dl, LHS.getValueType()), ISD::SETNE); in ExpandIntRes_UADDSUBO()
3838 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
3869 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
4385 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE); in ExpandIntRes_MULFIX()
4388 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE); in ExpandIntRes_MULFIX()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3339 case ISD::SETNE: { in get32BitZExtCompare()
3516 case ISD::SETNE: { in get32BitSExtCompare()
3683 case ISD::SETNE: { in get64BitZExtCompare()
3842 case ISD::SETNE: { in get64BitSExtCompare()
4128 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4172 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4221 case ISD::SETNE: in SelectCC()
4248 case ISD::SETNE: in SelectCC()
4299 case ISD::SETNE: in getPredicateForSetCC()
4340 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
[all …]
H A DPPCInstrInfo.td3586 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3657 defm : ExtSetCCPat<SETNE,
3751 defm : ExtSetCCShiftPat<SETNE,
3859 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3861 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3864 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3876 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3888 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3890 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3893 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
[all …]
H A DPPCInstrP10.td1979 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1990 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
1992 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
2007 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2030 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2037 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td323 def BNE : Branch_RR<0x09, "bne", SETNE>;
330 def BNEI : Branch_RI<0x06, "bnei", SETNE>;
337 def BNEZ : Branch_RZ<0x01, 0x01, "bnez", SETNE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td366 defm : BRCond_Bin<SETNE, "FCMPNE", BT32, BF32, MVC32>;
424 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)), bb:$imm16),
426 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)),
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td349 def COND_ONE : PatFrags<(ops), [(OtherVT SETONE), (OtherVT SETNE)]>;
370 def COND_UNE_NE : PatFrags<(ops), [(OtherVT SETUNE), (OtherVT SETNE)]>;
386 def COND_NE : PatFrags<(ops), [(OtherVT SETNE), (OtherVT SETUNE)]>;
H A DR600ISelLowering.cpp899 case ISD::SETNE: in LowerSELECT_CC()
937 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1862 case ISD::SETNE: return LHS; in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1737 case ISD::SETNE: in TranslateIntegerM68kCC()
1825 case ISD::SETNE: in TranslateM68kCC()
2157 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2168 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2174 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1); in LowerSETCC()
2187 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2361 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerSELECT()
2590 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerBRCOND()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td74 defm NE : ComparisonInt<SETNE, "ne ", 0x47, 0x52>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp536 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE }, in ARMTargetLowering()
537 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE }, in ARMTargetLowering()
538 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE }, in ARMTargetLowering()
539 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE }, in ARMTargetLowering()
540 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE }, in ARMTargetLowering()
541 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE }, in ARMTargetLowering()
542 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE }, in ARMTargetLowering()
545 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE }, in ARMTargetLowering()
546 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE }, in ARMTargetLowering()
547 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE }, in ARMTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp448 return DAG.getSetCC(DL, BoolVecTy, BCVec, ZeroVec, ISD::CondCode::SETNE); in getMaskBroadcast()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1413 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1419 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1426 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1432 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1505 X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
1522 X86_INTRINSIC_DATA(sse_ucomineq_ss, COMI, X86ISD::UCOMI, ISD::SETNE),
1530 X86_INTRINSIC_DATA(sse2_comineq_sd, COMI, X86ISD::COMI, ISD::SETNE),
1577 X86_INTRINSIC_DATA(sse2_ucomineq_sd, COMI, X86ISD::UCOMI, ISD::SETNE),
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp200 { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE }, in MSP430TargetLowering()
206 { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE }, in MSP430TargetLowering()
1058 case ISD::SETNE: in EmitCMP()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat64InstrInfo.td168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1523 case ISD::SETNE: in intCondCCodeToRcond()
1542 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1561 case ISD::SETNE: in FPCondCCodeToFCC()
2079 if (isNullConstant(RHS) && CC == ISD::SETNE && in LookThroughSetCC()
3197 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
3200 ISD::SETNE); in LowerUMULO_SMULO()

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