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Searched refs:SETLT (Results 1 – 25 of 70) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
184 def : PatFPSetcc<SETLT, FCMP_CLT_D, FPR64>;
196 defm : PatFPBrcond<SETLT, FCMP_CLT_D, FPR64>;
210 def : PatStrictFsetccs<SETLT, FCMP_SLT_D, FPR64>;
H A DLoongArchFloat32InstrInfo.td195 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
208 def : PatFPSetcc<SETLT, FCMP_CLT_S, FPR32>;
228 defm : PatFPBrcond<SETLT, FCMP_CLT_S, FPR32>;
245 def : PatStrictFsetccs<SETLT, FCMP_SLT_S, FPR32>;
H A DLoongArchISelDAGToDAG.h79 case ISD::SETLT: in getBranchOpcForIntCC()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1708 SETLT, // 1 X 1 0 0 True if less than enumerator
1719 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h77 case ISD::SETLT: in intCondCode2Icc()
109 case ISD::SETLT: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfa.td262 def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S, f32>;
287 def: PatSetCC<FPR64, strict_fsetcc, SETLT, FLTQ_D, f64>;
317 def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H, f16>;
H A DRISCVInstrInfoD.td408 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
415 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_D, Ext>;
435 def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D, f64>;
455 def : PatSetCC<FPR64INX, any_fsetccs, SETLT, FLT_D_INX, f64>;
475 def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64>;
H A DRISCVInstrInfoXqci.td1444 def : BcciPat<SETLT, QC_BLTI, simm5nonzero>;
1451 def : Bcci48Pat<SETLT, QC_E_BLTI, simm16nonzero>;
1458 def : SelectQCbi<SETLT, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1465 def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1505 def : QCIMVCCPat <SETLT, QC_MVLT>;
1508 def : QCIMVCCIPat <SETLT, QC_MVLTI, simm5>;
1521 def : QCILICCPat <SETLT, QC_LILT>;
1528 def : QCILICCIPat <SETLT, QC_LILTI, simm5>;
1536 def : QCILICCPatInv <SETLT, QC_LIGE>;
1543 def : QCILICCIPatInv <SETLT, QC_LIGEI, simm5>;
H A DRISCVISelDAGToDAG.h186 case ISD::SETLT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoZfh.td387 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
394 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_H, Ext>;
431 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_H, Ext>;
H A DRISCVInstrInfoVSDPatterns.td1026 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1033 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1037 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1045 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1048 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLE", SETLT, SETGT,
1384 defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
H A DRISCVInstrInfoF.td662 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
669 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_S, Ext>;
706 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_S, Ext>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp225 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
241 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
264 case ISD::SETLT: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td389 defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, BF32, MVC32>;
438 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
440 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)),
442 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td369 defm : BRCond_Bin<SETLT, "FCMPLT", BT32, BF32, MVC32>;
412 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
414 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp267 setCondCodeAction(ISD::SETLT, T, Expand); in initializeHVXLowering()
349 setCondCodeAction(ISD::SETLT, MVT::v64f16, Expand); in initializeHVXLowering()
364 setCondCodeAction(ISD::SETLT, MVT::v32f32, Expand); in initializeHVXLowering()
2461 DAG.getSetCC(dl, PredTy, And, getZero(dl, ResTy, DAG), ISD::SETLT); in emitHvxAddWithOverflow()
2627 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2628 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2637 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2679 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2680 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2693 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp668 case ISD::SETLT: in NegateCC()
979 SET_NEWCC(SETLT, JSLT); in EmitInstrWithCustomInserter()
990 CC == ISD::SETLT || in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp351 case ISD::SETLT: in softenSetCCOperands()
881 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyMultipleUseDemandedBits()
1766 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyDemandedBits()
4191 Cond == ISD::SETEQ ? ISD::SETGE : ISD::SETLT); in foldSetCCWithAnd()
4951 case ISD::SETLT: in SimplifySetCC()
5124 Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGE); in SimplifySetCC()
5176 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
5188 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
5303 ISD::SETLT); in SimplifySetCC()
5618 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
[all …]
H A DLegalizeIntegerTypes.cpp3432 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3487 DAG.getSetCC(DL, CCT, LHSH, DAG.getConstant(0, DL, NVT), ISD::SETLT); in ExpandIntRes_MINMAX()
3547 Pred = ISD::SETLT; in ExpandIntRes_MINMAX()
4023 DAG.getConstant(0, dl, NVT), ISD::SETLT); in ExpandIntRes_ABS()
4500 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT); in ExpandIntRes_MULFIX()
4647 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
4656 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT); in ExpandIntRes_MULFIX()
4660 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
4674 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT); in ExpandIntRes_MULFIX()
4769 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT); in ExpandIntRes_SADDSUBO()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3416 case ISD::SETLT: { in get32BitZExtCompare()
3595 case ISD::SETLT: { in get32BitSExtCompare()
3750 case ISD::SETLT: { in get64BitZExtCompare()
3910 case ISD::SETLT: { in get64BitSExtCompare()
4223 case ISD::SETLT: in SelectCC()
4250 case ISD::SETLT: in SelectCC()
4301 case ISD::SETLT: in getPredicateForSetCC()
4328 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
4365 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
4411 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3565 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3705 defm : ExtSetCCPat<SETLT,
3737 defm : ExtSetCCPat<SETLT,
3812 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3840 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3852 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3880 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3967 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
4011 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),
4038 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp824 case ISD::SETLT: in getBranchOpcode()
867 case ISD::SETLT: in getFPBranchKind()
1365 SDValue Cond = DAG.getSetCC(DL, VT, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
1415 SDValue Cond = DAG.getSetCC(DL, VT, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h624 X86_INTRINSIC_DATA(avx10_vcomisbf16lt, COMI, X86ISD::COMI, ISD::SETLT),
1914 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1938 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1946 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1993 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td76 defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1735 case ISD::SETLT: in TranslateIntegerM68kCC()
1765 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) { in TranslateM68kCC()
1769 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1820 case ISD::SETLT: in TranslateM68kCC()
3463 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3518 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()

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