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Searched refs:SETLT (Results 1 – 25 of 65) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td189 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
202 def : PatFPSetcc<SETLT, FCMP_CLT_S, FPR32>;
222 defm : PatFPBrcond<SETLT, FCMP_CLT_S, FPR32>;
239 def : PatStrictFsetccs<SETLT, FCMP_SLT_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td169 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
182 def : PatFPSetcc<SETLT, FCMP_CLT_D, FPR64>;
194 defm : PatFPBrcond<SETLT, FCMP_CLT_D, FPR64>;
208 def : PatStrictFsetccs<SETLT, FCMP_SLT_D, FPR64>;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1597 SETLT, // 1 X 1 0 0 True if less than enumerator
1608 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfa.td207 def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S, f32>;
230 def: PatSetCC<FPR64, strict_fsetcc, SETLT, FLTQ_D, f64>;
258 def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H, f16>;
H A DRISCVInstrInfoD.td397 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
404 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_D, Ext>;
424 def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D, f64>;
444 def : PatSetCC<FPR64INX, any_fsetccs, SETLT, FLT_D_INX, f64>;
464 def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64>;
H A DRISCVISelDAGToDAG.h177 case ISD::SETLT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td1027 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1034 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1038 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1046 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1049 defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
1380 defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
H A DRISCVInstrInfoZfh.td353 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
360 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_H, Ext>;
397 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_H, Ext>;
H A DRISCVInstrInfoF.td604 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
611 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_S, Ext>;
648 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_S, Ext>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp225 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
241 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
264 case ISD::SETLT: in getICmpCondCode()
H A DTargetLoweringBase.cpp592 CmpLibcallCCs[RTLIB::OLT_F32] = ISD::SETLT; in initCmpLibcallCCs()
593 CmpLibcallCCs[RTLIB::OLT_F64] = ISD::SETLT; in initCmpLibcallCCs()
594 CmpLibcallCCs[RTLIB::OLT_F128] = ISD::SETLT; in initCmpLibcallCCs()
595 CmpLibcallCCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in initCmpLibcallCCs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td325 def BLT : Branch_RR<0x02, "blt", SETLT>;
332 def BLTI : Branch_RI<0x0A, "blti", SETLT>;
339 def BLTZ : Branch_RZ<0x01, 0x02, "bltz", SETLT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td389 defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, BF32, MVC32>;
438 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
440 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)),
442 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td369 defm : BRCond_Bin<SETLT, "FCMPLT", BT32, BF32, MVC32>;
412 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
414 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp619 case ISD::SETLT: in NegateCC()
871 SET_NEWCC(SETLT, JSLT); in EmitInstrWithCustomInserter()
882 CC == ISD::SETLT || in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp263 setCondCodeAction(ISD::SETLT, T, Expand); in initializeHVXLowering()
343 setCondCodeAction(ISD::SETLT, MVT::v64f16, Expand); in initializeHVXLowering()
356 setCondCodeAction(ISD::SETLT, MVT::v32f32, Expand); in initializeHVXLowering()
2424 DAG.getSetCC(dl, PredTy, And, getZero(dl, ResTy, DAG), ISD::SETLT); in emitHvxAddWithOverflow()
2590 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2591 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2600 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2642 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2643 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2656 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp337 case ISD::SETLT: in softenSetCCOperands()
826 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyMultipleUseDemandedBits()
1719 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyDemandedBits()
4015 Cond == ISD::SETEQ ? ISD::SETGE : ISD::SETLT); in foldSetCCWithAnd()
4737 case ISD::SETLT: in SimplifySetCC()
4908 Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGE); in SimplifySetCC()
4960 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
4972 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
5087 ISD::SETLT); in SimplifySetCC()
5401 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
[all …]
H A DLegalizeIntegerTypes.cpp3249 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3290 DAG.getSetCC(DL, CCT, LHSH, DAG.getConstant(0, DL, NVT), ISD::SETLT); in ExpandIntRes_MINMAX()
3350 Pred = ISD::SETLT; in ExpandIntRes_MINMAX()
3825 DAG.getConstant(0, dl, NVT), ISD::SETLT); in ExpandIntRes_ABS()
4276 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT); in ExpandIntRes_MULFIX()
4423 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
4432 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT); in ExpandIntRes_MULFIX()
4436 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
4450 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT); in ExpandIntRes_MULFIX()
4545 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT); in ExpandIntRes_SADDSUBO()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3417 case ISD::SETLT: { in get32BitZExtCompare()
3596 case ISD::SETLT: { in get32BitSExtCompare()
3751 case ISD::SETLT: { in get64BitZExtCompare()
3911 case ISD::SETLT: { in get64BitSExtCompare()
4224 case ISD::SETLT: in SelectCC()
4251 case ISD::SETLT: in SelectCC()
4302 case ISD::SETLT: in getPredicateForSetCC()
4329 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
4366 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
4412 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3525 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3665 defm : ExtSetCCPat<SETLT,
3697 defm : ExtSetCCPat<SETLT,
3772 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3800 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3812 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3840 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3927 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
3971 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),
3998 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td76 defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1733 case ISD::SETLT: in TranslateIntegerM68kCC()
1763 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) { in TranslateM68kCC()
1767 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1818 case ISD::SETLT: in TranslateM68kCC()
3463 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3518 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1504 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1521 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1529 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1576 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, in MSP430TargetLowering()
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, in MSP430TargetLowering()
1110 case ISD::SETLT: in EmitCMP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td352 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
378 def COND_SLT : PatFrag<(ops), (OtherVT SETLT)>;

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