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Searched refs:SETGT (Results 1 – 25 of 56) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1595 SETGT, // 1 X 0 1 0 True if greater than enumerator
1608 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp227 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
243 case ICmpInst::ICMP_SGT: return ISD::SETGT; in getICmpCondCode()
268 case ISD::SETGT: in getICmpCondCode()
H A DTargetLoweringBase.cpp600 CmpLibcallCCs[RTLIB::OGT_F32] = ISD::SETGT; in initCmpLibcallCCs()
601 CmpLibcallCCs[RTLIB::OGT_F64] = ISD::SETGT; in initCmpLibcallCCs()
602 CmpLibcallCCs[RTLIB::OGT_F128] = ISD::SETGT; in initCmpLibcallCCs()
603 CmpLibcallCCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in initCmpLibcallCCs()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3390 case ISD::SETGT: { in get32BitZExtCompare()
3571 case ISD::SETGT: { in get32BitSExtCompare()
3728 case ISD::SETGT: { in get64BitZExtCompare()
3889 case ISD::SETGT: { in get64BitSExtCompare()
4232 case ISD::SETGT: in SelectCC()
4259 case ISD::SETGT: in SelectCC()
4308 case ISD::SETGT: in getPredicateForSetCC()
4331 case ISD::SETGT: return 1; // Bit #1 = SETOGT in getCRIdxForSetCC()
4366 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
4390 case ISD::SETGT: in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3581 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3681 defm : ExtSetCCPat<SETGT,
3713 defm : ExtSetCCPat<SETGT,
3776 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3804 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3816 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3844 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3931 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
3975 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)),
4002 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)),
[all …]
H A DPPCInstrSPE.td844 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
865 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td390 defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, BF32, MVC32>;
450 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
452 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)),
454 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td370 defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, BF32, MVC32>;
420 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
422 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)),
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp96 setCondCodeAction(ISD::SETGT, MVT::i32, Expand); in XtensaTargetLowering()
535 case ISD::SETGT: in getBranchOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td78 defm GT_S : ComparisonInt<SETGT, "gt_s", 0x4a, 0x55>;
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp865 SET_NEWCC(SETGT, JSGT); in EmitInstrWithCustomInserter()
880 bool isSignedCmp = (CC == ISD::SETGT || in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td119 [{return (N->getZExtValue() == ISD::SETGT);}]>;
139 [{return (N->getZExtValue() == ISD::SETGT);}]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td1027 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1034 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1038 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1046 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1049 defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
H A DRISCVInstrInfoVVLPatterns.td2319 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
2326 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
2330 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
2338 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
2341 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1502 X86_INTRINSIC_DATA(sse_comigt_ss, COMI, X86ISD::COMI, ISD::SETGT),
1519 X86_INTRINSIC_DATA(sse_ucomigt_ss, COMI, X86ISD::UCOMI, ISD::SETGT),
1527 X86_INTRINSIC_DATA(sse2_comigt_sd, COMI, X86ISD::COMI, ISD::SETGT),
1574 X86_INTRINSIC_DATA(sse2_ucomigt_sd, COMI, X86ISD::UCOMI, ISD::SETGT),
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp204 { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT }, in MSP430TargetLowering()
210 { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT }, in MSP430TargetLowering()
1107 case ISD::SETGT: in EmitCMP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td350 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
376 def COND_SGT : PatFrag<(ops), (OtherVT SETGT)>;
H A DR600Instructions.td746 0x09, "SETGT",
865 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
1722 def : CND_INT_f32 <CNDGT_INT, SETGT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat64InstrInfo.td168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp349 case ISD::SETGT: in softenSetCCOperands()
4733 case ISD::SETGT: in SimplifySetCC()
4940 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
4990 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
5095 ISD::SETGT); in SimplifySetCC()
5394 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y in SimplifySetCC()
8230 ISD::SETGT); in expandFP_TO_SINT()
8402 ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in createSelectForFMINNUM_FMAXNUM()
8502 DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT); in expandFMINIMUM_FMAXIMUM()
8765 PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, InfV, ISD::SETGT); in expandIS_FPCLASS()
[all …]
H A DLegalizeIntegerTypes.cpp3245 return std::make_pair(ISD::SETGT, ISD::UMAX); in getExpandedMinMaxOps()
3344 Pred = ISD::SETGT; in ExpandIntRes_MINMAX()
4417 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT); in ExpandIntRes_MULFIX()
4430 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT); in ExpandIntRes_MULFIX()
4449 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT); in ExpandIntRes_MULFIX()
5347 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1 in IntegerExpandSetCCOperands()
5359 case ISD::SETGT: in IntegerExpandSetCCOperands()
5428 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
H A DSelectionDAGDumper.cpp518 case ISD::SETGT: return "setgt"; in getOperationName()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp56 case ISD::SETGT: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1729 case ISD::SETGT: in TranslateIntegerM68kCC()
1758 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) { in TranslateM68kCC()
1810 case ISD::SETGT: in TranslateM68kCC()

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