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Searched refs:SETGE (Results 1 – 25 of 63) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1707 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator
1719 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.h81 case ISD::SETGE: in getBranchOpcForIntCC()
H A DLoongArchFloat64InstrInfo.td170 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat32InstrInfo.td194 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchISelLowering.cpp180 ISD::SETGE, ISD::SETNE, ISD::SETGT}; in LoongArchTargetLowering()
307 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
327 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering()
374 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
394 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering()
710 CC = CC == ISD::SETEQ ? ISD::SETGE : ISD::SETLT; in translateSetCCForBranch()
733 CC = ISD::SETGE; in translateSetCCForBranch()
742 CC = ISD::SETGE; in translateSetCCForBranch()
4608 case ISD::SETGE: in performSETCC_BITCASTCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h83 case ISD::SETGE: in intCondCode2Icc()
118 case ISD::SETGE: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp228 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
239 case ICmpInst::ICMP_SGE: return ISD::SETGE; in getICmpCondCode()
260 case ISD::SETGE: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td388 defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, BF32, MVC32>;
432 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
434 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)),
436 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td368 defm : BRCond_Bin<SETGE, "FCMPHS", BT32, BF32, MVC32>;
408 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
410 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)),
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h188 case ISD::SETGE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoXqci.td1445 def : BcciPat<SETGE, QC_BGEI, simm5nonzero>;
1452 def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
1459 def : SelectQCbi<SETGE, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1466 def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1522 def : QCILICCPat <SETGE, QC_LIGE>;
1529 def : QCILICCIPat <SETGE, QC_LIGEI, simm5>;
1535 def : QCILICCPatInv <SETGE, QC_LILT>;
1542 def : QCILICCIPatInv <SETGE, QC_LILTI, simm5>;
H A DRISCVInstrInfoVSDPatterns.td1028 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLE", SETLE, SETGE>;
1035 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLE", SETLE, SETGE>;
1043 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLE", SETLE, SETGE>;
1052 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGE, SETLE,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h621 X86_INTRINSIC_DATA(avx10_vcomisbf16ge, COMI, X86ISD::COMI, ISD::SETGE),
1911 X86_INTRINSIC_DATA(sse_comige_ss, COMI, X86ISD::COMI, ISD::SETGE),
1935 X86_INTRINSIC_DATA(sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE),
1943 X86_INTRINSIC_DATA(sse2_comige_sd, COMI, X86ISD::COMI, ISD::SETGE),
1990 X86_INTRINSIC_DATA(sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE),
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp975 SET_NEWCC(SETGE, JSGE); in EmitInstrWithCustomInserter()
989 CC == ISD::SETGE || in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td82 defm GE_S : ComparisonInt<SETGE, "ge_s", 0x4e, 0x59>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td3605 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3713 defm : ExtSetCCPat<SETGE,
3745 defm : ExtSetCCPat<SETGE,
3893 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3910 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3922 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3939 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3952 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
4024 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)),
4051 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)),
[all …]
H A DPPCISelDAGToDAG.cpp3352 case ISD::SETGE: { in get32BitZExtCompare()
3536 case ISD::SETGE: { in get32BitSExtCompare()
3695 case ISD::SETGE: { in get64BitZExtCompare()
3854 case ISD::SETGE: { in get64BitSExtCompare()
4224 case ISD::SETGE: in SelectCC()
4251 case ISD::SETGE: in SelectCC()
4310 case ISD::SETGE: in getPredicateForSetCC()
4335 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE in getCRIdxForSetCC()
4364 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break; in getVCmpInst()
4396 case ISD::SETGE: in getVCmpInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td351 def COND_OGE : PatFrags<(ops), [(OtherVT SETOGE), (OtherVT SETGE)]>;
377 def COND_SGE : PatFrag<(ops), (OtherVT SETGE)>;
H A DR600Instructions.td751 0xA, "SETGE",
870 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
1723 def : CND_INT_f32 <CNDGE_INT, SETGE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp567 case ISD::SETGE: in intCCToAVRCC()
648 CC = ISD::SETGE; in getAVRCmp()
673 CC = ISD::SETGE; in getAVRCmp()
692 CC = ISD::SETGE; in getAVRCmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td323 def BGE : Branch_RR<0x0A, "bge", SETGE>;
330 def BGEI : Branch_RI<0x0E, "bgei", SETGE>;
337 def BGEZ : Branch_RZ<0x01, 0x03, "bgez", SETGE>;
H A DXtensaISelLowering.cpp830 case ISD::SETGE: in getBranchOpcode()
870 case ISD::SETGE: in getFPBranchKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp831 case ISD::SETGE: in IntCondCCodeToICC()
1225 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp59 case ISD::SETGE: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp541 case ISD::SETGE: return "setge"; in getOperationName()

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