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Searched refs:SETEQ (Results 1 – 25 of 72) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td73 defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td397 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
402 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_D, Ext>;
412 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
419 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),
432 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)),
439 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETEQ)),
452 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)),
459 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETEQ)),
H A DRISCVISelDAGToDAG.h100 return selectSETCC(N, ISD::SETEQ, Val); in selectSETEQ()
173 case ISD::SETEQ: in getRISCVCCForIntCC()
H A DRISCVInstrInfoZfh.td353 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
358 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_H, Ext>;
368 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETEQ)),
375 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETEQ)),
383 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETEQ)),
390 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETEQ)),
H A DRISCVInstrInfoF.td604 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
609 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_S, Ext>;
619 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
626 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ)),
634 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ)),
641 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETEQ)),
H A DRISCVInstrInfoVSDPatterns.td1024 defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
1032 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
1042 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
1374 defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1594 SETEQ, // 1 X 0 0 1 True if equal enumerator
1620 return Code == SETEQ || Code == SETNE; in isIntEqualitySetCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp319 case ISD::SETEQ: in softenSetCCOperands()
3985 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithAnd()
4015 Cond == ISD::SETEQ ? ISD::SETGE : ISD::SETLT); in foldSetCCWithAnd()
4105 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
4107 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
4168 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4241 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"); in foldSetCCWithBinOp()
4312 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4317 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) { in simplifySetCCWithCTPOP()
4340 ISD::CondCode CmpCond = Cond == ISD::SETEQ ? ISD::SETUGT : ISD::SETULE; in simplifySetCCWithCTPOP()
[all …]
H A DLegalizeIntegerTypes.cpp2855 N->getOperand(2), ISD::SETEQ); in ExpandIntegerResult()
3184 ISD::SETEQ); in ExpandShiftWithUnknownAmountBit()
3323 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ); in ExpandIntRes_MINMAX()
3478 DAG.getConstant(0, dl, NVT), ISD::SETEQ); in ExpandIntRes_ADDSUB()
3482 DAG.getConstant(0, dl, NVT), ISD::SETEQ); in ExpandIntRes_ADDSUB()
3618 DAG.getConstant(0, dl, Lo.getValueType()), ISD::SETEQ); in ExpandIntRes_UADDSUBO()
4418 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ); in ExpandIntRes_MULFIX()
4424 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ); in ExpandIntRes_MULFIX()
4431 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ); in ExpandIntRes_MULFIX()
4437 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ); in ExpandIntRes_MULFIX()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp223 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
235 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
252 case ISD::SETEQ: in getICmpCondCode()
H A DTargetLoweringBase.cpp580 CmpLibcallCCs[RTLIB::OEQ_F32] = ISD::SETEQ; in initCmpLibcallCCs()
581 CmpLibcallCCs[RTLIB::OEQ_F64] = ISD::SETEQ; in initCmpLibcallCCs()
582 CmpLibcallCCs[RTLIB::OEQ_F128] = ISD::SETEQ; in initCmpLibcallCCs()
583 CmpLibcallCCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in initCmpLibcallCCs()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3327 case ISD::SETEQ: { in get32BitZExtCompare()
3501 case ISD::SETEQ: { in get32BitSExtCompare()
3672 case ISD::SETEQ: { in get64BitZExtCompare()
3829 case ISD::SETEQ: { in get64BitSExtCompare()
4128 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4172 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4220 case ISD::SETEQ: in SelectCC()
4247 case ISD::SETEQ: in SelectCC()
4296 case ISD::SETEQ: in getPredicateForSetCC()
4333 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
[all …]
H A DPPCInstrInfo.td3551 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3649 defm : ExtSetCCPat<SETEQ,
3759 defm : ExtSetCCShiftPat<SETEQ,
3778 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3780 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3794 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3806 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3818 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3820 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3834 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td322 def BEQ : Branch_RR<0x01, "beq", SETEQ>;
329 def BEQI : Branch_RI<0x02, "beqi", SETEQ>;
336 def BEQZ : Branch_RZ<0x01, 0x00, "beqz", SETEQ>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td387 defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
470 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
472 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)),
474 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td367 defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, BT32, MVCV32>;
428 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
430 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)),
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td189 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
191 def : PatFPSetcc<SETEQ, FCMP_CEQ_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td169 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
171 def : PatFPSetcc<SETEQ, FCMP_CEQ_D, FPR64>;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1669 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1727 case ISD::SETEQ: in TranslateIntegerM68kCC()
1806 case ISD::SETEQ: in TranslateM68kCC()
2157 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2168 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2187 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2461 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && in LowerBRCOND()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp812 case ISD::SETEQ: in IntCondCCodeToICC()
1260 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS()
1317 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSRL_PARTS()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1410 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1416 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1423 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1429 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1500 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ),
1517 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ),
1525 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ),
1572 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp199 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ }, in MSP430TargetLowering()
205 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ }, in MSP430TargetLowering()
1051 case ISD::SETEQ: in EmitCMP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td348 def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;
385 def COND_EQ : PatFrags<(ops), [(OtherVT SETEQ), (OtherVT SETUEQ)]>;
H A DAMDGPUISelDAGToDAG.cpp2398 return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64(); in isCBranchSCC()
2416 if ((VCMP_CC == ISD::SETEQ || VCMP_CC == ISD::SETNE) && in combineBallotPattern()
2424 Negate = VCMP_CC == ISD::SETEQ; in combineBallotPattern()
2451 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && in SelectBRCOND()
2462 Negate = CC == ISD::SETEQ; in SelectBRCOND()

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