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Searched refs:SETEQ (Results 1 – 25 of 77) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h102 return selectSETCC(N, ISD::SETEQ, Val); in selectSETEQ()
182 case ISD::SETEQ: in getRISCVCCForIntCC()
H A DRISCVInstrInfoD.td408 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
413 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_D, Ext>;
423 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
430 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),
443 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)),
450 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETEQ)),
463 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs2, SETEQ)),
470 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs1, SETEQ)),
H A DRISCVInstrInfoXqci.td1442 def : BcciPat<SETEQ, QC_BEQI, simm5nonzero>;
1449 def : Bcci48Pat<SETEQ, QC_E_BEQI, simm16nonzero>;
1456 def : SelectQCbi<SETEQ, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1463 def : SelectQCbi<SETEQ, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1503 def : QCIMVCCPat <SETEQ, QC_MVEQ>;
1514 def : QCIMVCCIPat <SETEQ, QC_MVEQI, simm5>;
1519 def : QCILICCPat <SETEQ, QC_LIEQ>;
1526 def : QCILICCIPat <SETEQ, QC_LIEQI, simm5>;
1534 def : QCILICCPatInv <SETEQ, QC_LINE>;
1541 def : QCILICCIPatInv <SETEQ, QC_LINEI, simm5>;
[all …]
H A DRISCVInstrInfoZfh.td387 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
392 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_H, Ext>;
402 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETEQ)),
409 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETEQ)),
417 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETEQ)),
424 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETEQ)),
H A DRISCVInstrInfoXAndes.td729 def : NDS_BBPat<SETEQ, NDS_BBC>;
732 def : SelectNDS_BB<SETEQ>;
735 def : NDS_BCPat<SETEQ, NDS_BEQC>;
738 def : SelectNDS_BC<SETEQ>;
H A DRISCVInstrInfoF.td662 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
667 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_S, Ext>;
677 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
684 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ)),
692 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ)),
699 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs1, SETEQ)),
H A DRISCVInstrInfoVSDPatterns.td1023 defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
1031 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
1041 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
1378 defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.h75 case ISD::SETEQ: in getBranchOpcForIntCC()
H A DLoongArchFloat64InstrInfo.td171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
173 def : PatFPSetcc<SETEQ, FCMP_CEQ_D, FPR64>;
H A DLoongArchFloat32InstrInfo.td195 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
197 def : PatFPSetcc<SETEQ, FCMP_CEQ_S, FPR32>;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1705 SETEQ, // 1 X 0 0 1 True if equal enumerator
1731 return Code == SETEQ || Code == SETNE; in isIntEqualitySetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td73 defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp333 case ISD::SETEQ: in softenSetCCOperands()
450 assert(CCCode == (ShouldInvertCC ? ISD::SETEQ : ISD::SETNE) && in softenSetCCOperands()
4161 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithAnd()
4191 Cond == ISD::SETEQ ? ISD::SETGE : ISD::SETLT); in foldSetCCWithAnd()
4257 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithOr()
4317 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
4319 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
4379 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4451 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"); in foldSetCCWithBinOp()
4522 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
[all …]
H A DLegalizeIntegerTypes.cpp3038 N->getOperand(2), ISD::SETEQ); in ExpandIntegerResult()
3367 ISD::SETEQ); in ExpandShiftWithUnknownAmountBit()
3520 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ); in ExpandIntRes_MINMAX()
3674 DAG.getConstant(0, dl, NVT), ISD::SETEQ); in ExpandIntRes_ADDSUB()
3678 DAG.getConstant(0, dl, NVT), ISD::SETEQ); in ExpandIntRes_ADDSUB()
3816 DAG.getConstant(0, dl, Lo.getValueType()), ISD::SETEQ); in ExpandIntRes_UADDSUBO()
4642 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ); in ExpandIntRes_MULFIX()
4648 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ); in ExpandIntRes_MULFIX()
4655 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ); in ExpandIntRes_MULFIX()
4661 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ); in ExpandIntRes_MULFIX()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h73 case ISD::SETEQ: in intCondCode2Icc()
103 case ISD::SETEQ: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp223 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
235 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
252 case ISD::SETEQ: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3326 case ISD::SETEQ: { in get32BitZExtCompare()
3500 case ISD::SETEQ: { in get32BitSExtCompare()
3671 case ISD::SETEQ: { in get64BitZExtCompare()
3828 case ISD::SETEQ: { in get64BitSExtCompare()
4127 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4171 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4219 case ISD::SETEQ: in SelectCC()
4246 case ISD::SETEQ: in SelectCC()
4295 case ISD::SETEQ: in getPredicateForSetCC()
4332 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
[all …]
H A DPPCInstrInfo.td3591 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3689 defm : ExtSetCCPat<SETEQ,
3799 defm : ExtSetCCShiftPat<SETEQ,
3818 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3820 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3834 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3846 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3858 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3860 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3874 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td387 defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, BT32, MVCV32, 1>;
470 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
472 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)),
474 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td367 defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, BT32, MVCV32>;
428 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
430 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)),
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1671 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1729 case ISD::SETEQ: in TranslateIntegerM68kCC()
1808 case ISD::SETEQ: in TranslateM68kCC()
2159 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2170 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2189 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2462 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && in LowerBRCOND()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp801 case ISD::SETEQ: in IntCondCCodeToICC()
1214 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS()
1271 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSRL_PARTS()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h620 X86_INTRINSIC_DATA(avx10_vcomisbf16eq, COMI, X86ISD::COMI, ISD::SETEQ),
1910 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ),
1934 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ),
1942 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ),
1989 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td1410 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1416 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1423 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1429 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td348 def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;
385 def COND_EQ : PatFrags<(ops), [(OtherVT SETEQ), (OtherVT SETUEQ)]>;

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