Searched refs:SDWA (Results 1 – 17 of 17) sorted by relevance
116 using namespace AMDGPU::SDWA;410 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()417 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 && in convertToSDWA()418 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) { in convertToSDWA()484 getDstSel() != AMDGPU::SDWA::DWORD) { in convertToSDWA()1114 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()1124 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); in convertToSDWA()1134 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()1144 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()1151 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
38 SDWA = 2, enumerator75 SDWA = 1 << 14, enumerator337 SDWA = 2, enumerator876 namespace SDWA {
497 def SDWA {535 // GFX9 adds two features to SDWA:536 // 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.540 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This546 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA548 // gfx9 SDWA basic encoding568 // gfx9 SDWA-A581 // gfx9 SDWA-B608 let SDWA = 1;617 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,[all …]
34 field bit SDWA = 0;175 let TSFlags{14} = SDWA;259 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
462 "Support SDWA (Sub-DWORD Addressing) extension"468 "Support OMod with SDWA (Sub-DWORD Addressing) extension"474 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"480 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"486 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"492 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"1703 string SDWA = "SDWA";1727 let Name = AMDGPUAsmVariants.SDWA;
24 int SDWA = 2;1534 // instructions with SDWA extension1693 // Return type of input modifiers operand specified input operand for SDWA1917 // Ins for SDWA1965 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions1970 // Outs for SDWA2202 0, // NumSrcArgs == 3 - No SDWA for VOP32204 0, // 64-bit dst - No SDWA for 64-bit operands2234 // Function that checks if instruction supports DPP and SDWA2719 // Maps ordinary instructions to their SDWA counterparts[all …]
513 return MI.getDesc().TSFlags & SIInstrFlags::SDWA; in isSDWA()517 return get(Opcode).TSFlags & SIInstrFlags::SDWA; in isSDWA()
1017 .addImm(DstLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()1018 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()1019 .addImm(AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) in copyPhysReg()1020 .addImm(SrcLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()1021 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()4849 DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) { in verifyInstruction()9241 if (get(Opcode).TSFlags & SIInstrFlags::SDWA) { in pseudoToMCOpcode()9244 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
122 // We only want to set this on the basic, non-SDWA or DPP forms.626 (inst_sdwa 0, $src, 0, 0, SDWA.WORD_1),
2249 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel in selectG_TRUNC()2250 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_TRUNC()2251 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel in selectG_TRUNC()
922 if (DstSel->getImm() == AMDGPU::SDWA::DWORD) in checkVALUHazards()
1355 // (they do not support SDWA or DPP).
911 // SDWA sext is the only modifier allowed.
485 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()515 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
397 else if (Flags & SIInstrFlags::SDWA) in printVOPDst()1192 using namespace llvm::AMDGPU::SDWA; in printSDWASel()1231 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
722 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA) in getInstruction()1670 using namespace AMDGPU::SDWA; in decodeSDWASrc()1718 using namespace AMDGPU::SDWA; in decodeSDWAVopcDst()
3464 (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) ) in checkTargetMatchPredicate()3473 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()3484 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, in getAllVariants()3508 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA, in getMatchedVariants()3720 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | SIInstrFlags::SDWA)) && in validateConstantBusLimitations()4058 if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc)) in validateMovrels()4345 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()4359 if (IsRevOpcode(Opcode) || (Desc.TSFlags & SIInstrFlags::SDWA)) in validateLdsDirect()9373 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()9402 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()[all …]