Searched refs:SDWA (Results 1 – 16 of 16) sorted by relevance
90 using namespace AMDGPU::SDWA;477 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()484 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 && in convertToSDWA()485 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) { in convertToSDWA()594 getDstSel() != AMDGPU::SDWA::DWORD) { in convertToSDWA()1282 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in createSDWAVersion()1285 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); in createSDWAVersion()1288 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in createSDWAVersion()1292 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in createSDWAVersion()
38 SDWA = 2, enumerator76 SDWA = 1 << 14, enumerator317 SDWA = 2, enumerator883 namespace SDWA {
34 field bit SDWA = 0;179 let TSFlags{14} = SDWA;264 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
625 def SDWA {663 // GFX9 adds two features to SDWA:664 // 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.668 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This674 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA676 // gfx9 SDWA basic encoding696 // gfx9 SDWA-A709 // gfx9 SDWA-B736 let SDWA = 1;744 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,[all …]
595 "Support SDWA (Sub-DWORD Addressing) extension"601 "Support OMod with SDWA (Sub-DWORD Addressing) extension"607 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"613 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"619 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"625 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"2025 string SDWA = "SDWA";2049 let Name = AMDGPUAsmVariants.SDWA;
24 int SDWA = 2;1777 // instructions with SDWA extension2018 // Return type of input modifiers operand specified input operand for SDWA2204 // Ins for SDWA2273 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions2278 // Outs for SDWA2486 0, // NumSrcArgs == 3 - No SDWA for VOP32488 0, // 64-bit dst - No SDWA for 64-bit operands2518 // Function that checks if instruction supports DPP and SDWA3099 // Maps ordinary instructions to their SDWA counterparts[all …]
532 return MI.getDesc().TSFlags & SIInstrFlags::SDWA; in isSDWA()536 return get(Opcode).TSFlags & SIInstrFlags::SDWA; in isSDWA()
1035 .addImm(DstLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()1036 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()1037 .addImm(AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) in copyPhysReg()1038 .addImm(SrcLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()1039 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()4954 if (Imm < 0 || Imm > AMDGPU::SDWA::SdwaSel::DWORD) { in verifyInstruction()5035 DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) { in verifyInstruction()9705 if (get(Opcode).TSFlags & SIInstrFlags::SDWA) { in pseudoToMCOpcode()9708 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
124 // We only want to set this on the basic, non-SDWA or DPP forms.662 (inst_sdwa 0, $src, 0, 0, SDWA.WORD_1),
2491 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel in selectG_TRUNC()2492 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_TRUNC()2493 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel in selectG_TRUNC()
897 if (DstSel->getImm() != AMDGPU::SDWA::DWORD) in getDstSelForwardingOperand()
1058 // SDWA sext is the only modifier allowed.
500 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()530 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
352 else if (Flags & SIInstrFlags::SDWA) in printVOPDst()1073 using namespace llvm::AMDGPU::SDWA; in printSDWASel()1112 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
874 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA) in getInstruction()1931 using namespace AMDGPU::SDWA; in decodeSDWASrc()1977 using namespace AMDGPU::SDWA; in decodeSDWAVopcDst()
3604 (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) ) in checkTargetMatchPredicate()3613 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()3631 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, in getAllVariants()3655 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA, in getMatchedVariants()3860 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | SIInstrFlags::SDWA)) && in validateConstantBusLimitations()4342 if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc)) in validateMovrels()4673 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()4687 if (IsRevOpcode(Opcode) || (Desc.TSFlags & SIInstrFlags::SDWA)) in validateLdsDirect()9994 using namespace llvm::AMDGPU::SDWA; in cvtSDWA()