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Searched refs:SDNode (Results 1 – 25 of 258) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.h81 bool IgnoreNodeResults(SDNode *N) const { in IgnoreNodeResults()
138 SmallVector<SDNode*, 128> Worklist;
178 void NoteDeletion(SDNode *Old, SDNode *New) { in NoteDeletion()
209 SDNode *AnalyzeNewNode(SDNode *N);
219 bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
220 bool CustomWidenLowerNode(SDNode *N, EVT VT);
225 SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
229 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
301 SDValue PromoteIntOpVectorReduction(SDNode *N, SDValue V);
304 void PromoteIntegerResult(SDNode *N, unsigned ResNo);
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H A DSelectionDAGPrinter.cpp37 return ((const SDNode *) Node)->getNumValues(); in numEdgeDestLabels()
41 return ((const SDNode *) Node)->getValueType(i).getEVTString(); in getEdgeDestLabel()
46 return itostr(I - SDNodeIterator::begin((const SDNode *) Node)); in getEdgeSourceLabel()
62 SDNode *TargetNode = *I; in getEdgeTarget()
76 static std::string getNodeIdentifierLabel(const SDNode *Node, in getNodeIdentifierLabel()
103 static std::string getSimpleNodeLabel(const SDNode *Node, in getSimpleNodeLabel()
112 std::string getNodeLabel(const SDNode *Node, const SelectionDAG *Graph);
113 static std::string getNodeAttributes(const SDNode *N, in getNodeAttributes()
137 std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, in getNodeLabel()
191 void SelectionDAG::setGraphAttrs(const SDNode *N, const char *Attrs) { in setGraphAttrs()
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H A DSDNodeDbgValue.h26 class SDNode; variable
43 SDNode *getSDNode() const { in getSDNode()
72 static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo) { in fromNode()
106 SDNode *Node; ///< Valid for expressions.
115 SDDbgOperand(SDNode *N, unsigned R) : kind(SDNODE) { in SDDbgOperand()
146 SDNode **AdditionalDependencies;
158 ArrayRef<SDDbgOperand> L, ArrayRef<SDNode *> Dependencies, in SDDbgValue()
163 AdditionalDependencies(Alloc.Allocate<SDNode *>(Dependencies.size())), in SDDbgValue()
195 SmallVector<SDNode *> getSDNodes() const { in getSDNodes()
196 SmallVector<SDNode *> Dependencies; in getSDNodes()
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H A DScheduleDAGSDNodes.cpp69 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) { in newSUnit()
111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, in CheckForPhysRegDependency()
144 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs, in CloneNodeWithValues()
165 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { in AddGlue()
166 SDNode *GlueDestNode = Glue.getNode(); in AddGlue()
190 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) { in RemoveUnusedGlue()
204 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) { in ClusterNeighboringLoads()
215 auto hasTiedInput = [this](const SDNode *N) { in ClusterNeighboringLoads()
227 SmallPtrSet<SDNode*, 16> Visited; in ClusterNeighboringLoads()
229 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode. in ClusterNeighboringLoads()
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H A DLegalizeFloatTypes.cpp51 void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { in SoftenFloatResult()
190 SDValue DAGTypeLegalizer::SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC) { in SoftenFloatRes_Unary()
209 SDValue DAGTypeLegalizer::SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC) { in SoftenFloatRes_Binary()
230 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) { in SoftenFloatRes_BITCAST()
234 SDValue DAGTypeLegalizer::SoftenFloatRes_FREEZE(SDNode *N) { in SoftenFloatRes_FREEZE()
240 SDValue DAGTypeLegalizer::SoftenFloatRes_ARITH_FENCE(SDNode *N) { in SoftenFloatRes_ARITH_FENCE()
247 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N, in SoftenFloatRes_MERGE_VALUES()
253 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) { in SoftenFloatRes_BUILD_PAIR()
262 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) { in SoftenFloatRes_ConstantFP()
286 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) { in SoftenFloatRes_EXTRACT_ELEMENT()
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H A DInstrEmitter.h51 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
54 void CreateVirtualRegisters(SDNode *Node,
93 void EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap, bool IsClone,
100 void EmitCopyToRegClassNode(SDNode *Node, VRBaseMapType &VRBaseMap);
104 void EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap, bool IsClone,
111 static unsigned CountResults(SDNode *Node);
142 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, in EmitNode()
162 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
164 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
H A DScheduleDAGFast.cpp204 SDNode *N = SU->getNode(); in CopyAndMoveSuccessors()
224 SmallVector<SDNode*, 2> NewNodes; in CopyAndMoveSuccessors()
232 SDNode *LoadNode = NewNodes[0]; in CopyAndMoveSuccessors()
370 SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(nullptr)); in InsertCopiesAndMoveSuccs()
374 SUnit *CopyToSU = newSUnit(static_cast<SDNode *>(nullptr)); in InsertCopiesAndMoveSuccs()
410 static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, in getPhysicalRegisterVT()
437 const SDNode *Node = nullptr) { in CheckForLiveRegDef()
479 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) { in DelayForLiveRegsBottomUp()
510 SDNode *SrcNode = Node->getOperand(2).getNode(); in DelayForLiveRegsBottomUp()
656 std::vector<SDNode*> Sequence;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.h57 void Select(SDNode *N) override;
76 MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
80 SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
82 void SelectFrameIndex(SDNode *N);
89 bool SelectBrevLdIntrinsic(SDNode *IntN);
90 bool SelectNewCircIntrinsic(SDNode *IntN);
91 void SelectLoad(SDNode *N);
94 void SelectStore(SDNode *N);
95 void SelectSHL(SDNode *N);
96 void SelectIntrinsicWChain(SDNode *N);
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H A DHexagonISelDAGToDAG.cpp195 MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) { in LoadInstrForLoadIntrinsic()
227 SDNode *HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, in StoreInstrForLoadIntrinsic()
228 SDNode *IntN) { in StoreInstrForLoadIntrinsic()
249 SDNode *StoreN; in StoreInstrForLoadIntrinsic()
283 SDNode *C = Ch.getNode(); in tryLoadOfLoadIntrinsic()
315 SDNode *S = StoreInstrForLoadIntrinsic(L, C); in tryLoadOfLoadIntrinsic()
329 bool HexagonDAGToDAGISel::SelectBrevLdIntrinsic(SDNode *IntN) { in SelectBrevLdIntrinsic()
370 bool HexagonDAGToDAGISel::SelectNewCircIntrinsic(SDNode *IntN) { in SelectNewCircIntrinsic()
456 void HexagonDAGToDAGISel::SelectLoad(SDNode *N) { in SelectLoad()
565 void HexagonDAGToDAGISel::SelectStore(SDNode *N) { in SelectStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h46 NVPTX::DivPrecisionLevel getDivF32Level(const SDNode *N) const;
47 bool usePrecSqrtF32(const SDNode *N) const;
71 void Select(SDNode *N) override;
72 bool tryIntrinsicChain(SDNode *N);
73 bool tryIntrinsicVoid(SDNode *N);
74 void SelectTexSurfHandle(SDNode *N);
75 bool tryLoad(SDNode *N);
76 bool tryLoadVector(SDNode *N);
77 bool tryLDU(SDNode *N);
79 bool tryStore(SDNode *N);
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td18 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
21 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
38 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
39 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
40 def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>;
41 def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>;
44 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
46 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 def X86strict_fmin : SDNode<"X86ISD::STRICT_FMIN", SDTFPBinOp,
51 def X86strict_fmax : SDNode<"X86ISD::STRICT_FMAX", SDTFPBinOp,
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H A DX86InstrFragments.td134 def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>;
137 def X86bsf : SDNode<"X86ISD::BSF", SDTBinaryArithWithFlags>;
138 def X86bsr : SDNode<"X86ISD::BSR", SDTBinaryArithWithFlags>;
139 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
140 def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
142 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
143 def X86fcmp : SDNode<"X86ISD::FCMP", SDTX86FCmp>;
144 def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>;
145 def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>;
146 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h48 static inline SDNode *packConstantV2I16(const SDNode *N, SelectionDAG &DAG) { in packConstantV2I16()
82 bool matchLoadD16FromBuildVector(SDNode *N) const;
84 void Select(SDNode *N) override;
88 void SelectBuildVector(SDNode *N, unsigned RegClassID);
89 void SelectVectorShuffle(SDNode *N);
94 bool isInlineImmediate(const SDNode *N) const;
104 bool isVGPRImm(const SDNode *N) const;
105 bool isUniformLoad(const SDNode *N) const;
106 bool isUniformBr(const SDNode *N) const;
110 bool isUnneededShiftMask(const SDNode *N, unsigned ShAmtBits) const;
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H A DAMDGPUInstrInfo.td65 def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
66 def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
67 def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
69 def callseq_start : SDNode<"ISD::CALLSEQ_START",
74 def callseq_end : SDNode<"ISD::CALLSEQ_END",
79 def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
89 def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN", AMDGPUTCReturnTP,
93 def AMDGPUtc_return_gfx: SDNode<"AMDGPUISD::TC_RETURN_GFX", AMDGPUTCReturnTP,
97 def AMDGPUtc_return_chain: SDNode<"AMDGPUISD::TC_RETURN_CHAIN",
103 def AMDGPUtc_return_chain_dvgpr: SDNode<"AMDGPUISD::TC_RETURN_CHAIN_DVGPR",
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H A DSIISelLowering.h176 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
178 SDValue performUCharToFloatCombine(SDNode *N,
180 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182 SDValue performSHLPtrCombine(SDNode *N,
193 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
194 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
195 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
196 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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H A DAMDGPUISelLowering.h107 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
108 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
109 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
110 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
115 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
116 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
118 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
120 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaOperators.td47 def Xtensa_call: SDNode<"XtensaISD::CALL", SDT_XtensaCall,
50 def Xtensa_callw8: SDNode<"XtensaISD::CALLW8", SDT_XtensaCall,
53 def Xtensa_ret: SDNode<"XtensaISD::RET", SDTNone,
56 def Xtensa_retw: SDNode<"XtensaISD::RETW", SDTNone,
59 def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, []>;
61 def Xtensa_callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_XtensaCallSeqStart,
64 def Xtensa_callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XtensaCallSeqEnd,
68 def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>;
70 def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC,
73 def Xtensa_srcl: SDNode<"XtensaISD::SRCL", SDT_XtensaSRC>;
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H A DXtensaISelDAGToDAG.cpp41 void Select(SDNode *Node) override;
136 void XtensaDAGToDAGISel::Select(SDNode *Node) { in Select()
154 SDNode *SSL = CurDAG->getMachineNode(Xtensa::SSL, DL, MVT::Glue, N1); in Select()
155 SDNode *SLL = in Select()
173 SDNode *EXTUI = CurDAG->getMachineNode( in Select()
180 SDNode *SSR = CurDAG->getMachineNode(Xtensa::SSR, DL, MVT::Glue, N1); in Select()
181 SDNode *SRL = in Select()
193 SDNode *SSR = CurDAG->getMachineNode(Xtensa::SSR, DL, MVT::Glue, N1); in Select()
194 SDNode *SRA = in Select()
205 SDNode *SSL = CurDAG->getMachineNode(Xtensa::SSL, DL, MVT::Glue, N2); in Select()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPInstrInfo.td1 //===-------------- VVPInstrInfo.td - VVP_* SDNode patterns ---------------===//
15 // The standard The VVP layer SDNode. The VE vector instruction.
16 // SDNode.
127 class vvp_commutative<SDNode RootOp> :
133 class vvp_fma_commutative<SDNode RootOp> :
140 def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>;
143 def vvp_sub : SDNode<"VEISD::VVP_SUB", SDTIntBinOpVVP>;
145 def vvp_mul : SDNode<"VEISD::VVP_MUL", SDTIntBinOpVVP>;
148 def vvp_sdiv : SDNode<"VEISD::VVP_SDIV", SDTIntBinOpVVP>;
149 def vvp_udiv : SDNode<"VEISD::VVP_UDIV", SDTIntBinOpVVP>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGISel.h108 virtual void Select(SDNode *N) = 0;
124 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
130 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
134 static void InvalidateNodeId(SDNode *N);
135 static int getUninvalidatedNodeId(SDNode *N);
137 static void EnforceNodeIdInvariant(SDNode *N);
376 void ReplaceUses(SDNode *F, SDNode *T) { in ReplaceUses()
382 void ReplaceNode(SDNode *F, SDNode *T) { in ReplaceNode()
442 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, in CheckComplexPattern()
444 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { in CheckComplexPattern()
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H A DSelectionDAGNodes.h68 class SDNode; variable
73 LLVM_ABI void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
92 LLVM_ABI bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
97 LLVM_ABI bool isConstantSplatVectorAllOnes(const SDNode *N,
103 LLVM_ABI bool isConstantSplatVectorAllZeros(const SDNode *N,
108 LLVM_ABI bool isBuildVectorAllOnes(const SDNode *N);
112 LLVM_ABI bool isBuildVectorAllZeros(const SDNode *N);
116 LLVM_ABI bool isBuildVectorOfConstantSDNodes(const SDNode *N);
120 LLVM_ABI bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
124 LLVM_ABI bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize,
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H A DSelectionDAG.h146 template <> struct ilist_alloc_traits<SDNode> {
147 static void deleteNode(SDNode *) {
168 using DbgValMapType = DenseMap<const SDNode *, SmallVector<SDDbgValue *, 2>>;
182 LLVM_ABI void erase(const SDNode *Node);
198 ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) const {
264 SDNode EntryNode;
270 ilist<SDNode> AllNodes;
274 using NodeAllocatorType = RecyclingAllocator<BumpPtrAllocator, SDNode,
283 FoldingSet<SDNode> CSEMap;
304 DenseMap<const SDNode *, NodeExtraInfo> SDEI;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td46 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
353 class SDNode<string opcode, SDTypeProfile typeprof,
354 list<SDNodeProperty> props = [], string sdclass = "SDNode">
370 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
371 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
372 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
373 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
374 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
375 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
376 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td261 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
263 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
266 def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>;
269 def z_retglue : SDNode<"SystemZISD::RET_GLUE", SDTNone,
271 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
274 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
277 def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall,
280 def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall,
283 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
284 def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET",
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h42 void Select(SDNode *Node) override;
79 bool tryShrinkShlLogicImm(SDNode *Node);
80 bool trySignedBitfieldExtract(SDNode *Node);
81 bool trySignedBitfieldInsertInSign(SDNode *Node);
82 bool trySignedBitfieldInsertInMask(SDNode *Node);
83 bool tryUnsignedBitfieldExtract(SDNode *Node, const SDLoc &DL, MVT VT,
85 bool tryUnsignedBitfieldInsertInZero(SDNode *Node, const SDLoc &DL, MVT VT,
87 bool tryIndexedLoad(SDNode *Node);
128 bool orDisjoint(const SDNode *Node) const;
129 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
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