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Searched refs:SCALAR_TO_VECTOR (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp111 case ISD::SCALAR_TO_VECTOR: in Select()
H A DSIISelLowering.cpp330 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
362 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
363 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
376 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
377 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v6i32); in SITargetLowering()
390 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
391 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32); in SITargetLowering()
404 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
405 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32); in SITargetLowering()
418 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
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H A DAMDGPUISelDAGToDAG.cpp239 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo); in matchLoadD16FromBuildVector()
479 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); in SelectBuildVector()
548 case ISD::SCALAR_TO_VECTOR: in Select()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h634 SCALAR_TO_VECTOR, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp68 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
298 SDValue OtherVal = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, OtherVT, in ScalarizeVecRes_FFREXP()
375 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo)); in ScalarizeVecRes_OverflowOp()
854 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
871 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_UnaryOp_StrictFP()
937 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
968 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_ROUND()
983 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_ROUND()
997 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
1012 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLo in ScalarizeVecOp_STRICT_FP_EXTEND()
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H A DLegalizeDAG.cpp394 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
1865 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V); in ExpandBVWithShuffles()
1973 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
2028 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
2031 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
3468 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
5717 case ISD::SCALAR_TO_VECTOR: { in PromoteNode()
H A DSelectionDAGDumper.cpp331 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; in getOperationName()
H A DDAGCombiner.cpp1960 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); in visit()
5873 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && in hoistLogicOpWithSameOpcodeHands()
22194 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
22573 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22660 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22804 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
24209 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
24243 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar); in visitCONCAT_VECTORS()
25145 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
25815 SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO); in visitVECTOR_SHUFFLE()
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H A DLegalizeIntegerTypes.cpp142 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
1933 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
5266 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
H A DTargetLowering.cpp1164 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedBits()
3105 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedVectorElts()
3236 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && DemandedElts == 1) in SimplifyDemandedVectorElts()
3238 Op, TLO.DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAG.cpp3341 case ISD::SCALAR_TO_VECTOR: { in computeKnownBits()
5323 case ISD::SCALAR_TO_VECTOR: in canCreateUndefOrPoison()
6158 case ISD::SCALAR_TO_VECTOR: in getNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp257 case ISD::SCALAR_TO_VECTOR: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1170 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
1649 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
2011 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
2240 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32f16, Custom); in X86TargetLowering()
2282 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8f16, Legal); in X86TargetLowering()
2283 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16f16, Custom); in X86TargetLowering()
2508 ISD::SCALAR_TO_VECTOR, in X86TargetLowering()
4955 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetConstantBitsFromNode()
5693 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetShuffleAndZeroables()
6003 case ISD::SCALAR_TO_VECTOR: in getFauxShuffleMask()
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H A DX86ISelLoweringCall.cpp820 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, in LowerReturn()
1063 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, ValReturned); in lowerRegToMasks()
1405 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val) in LowerMemArgument()
2183 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); in LowerCall()
H A DX86ISelDAGToDAG.cpp1271 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1273 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
H A DX86FastISel.cpp2639 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp879 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
986 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
1001 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
1004 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
1008 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
1009 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
1010 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
1011 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
3038 UI->getOpcode() != ISD::SCALAR_TO_VECTOR && in usePartialVectorLoads()
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H A DPPCISelDAGToDAG.cpp5959 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR && in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp443 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in SystemZTargetLowering()
560 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in SystemZTargetLowering()
5585 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
5851 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
5875 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerVECTOR_SHUFFLE()
6047 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerShift()
6219 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1129 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR); in AArch64TargetLowering()
2086 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, PreferNEON ? Legal : Expand); in addTypeForFixedLengthSVE()
5690 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, N); in LowerINTRINSIC_WO_CHAIN()
6582 SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load); in LowerLOAD()
13169 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) in LowerVECTOR_SHUFFLE()
14073 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
14365 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0); in LowerBUILD_VECTOR()
20495 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, Op1); in performAddSubIntoVectorOp()
20498 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, Op0); in performAddSubIntoVectorOp()
20888 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op); in tryCombineShiftImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp348 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in addMVEVectorTypes()
415 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in addMVEVectorTypes()
461 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in addMVEVectorTypes()
6059 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
6061 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
8041 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
8840 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { in LowerVECTOR_SHUFFLE()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td788 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp754 ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
879 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1021 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1163 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in RISCVTargetLowering()
6415 case ISD::SCALAR_TO_VECTOR: { in LowerOperation()
6421 SDValue V = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, WideVT, Scalar); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1662 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()