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Searched refs:SCALAR_TO_VECTOR (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp112 case ISD::SCALAR_TO_VECTOR: in Select()
H A DSIISelLowering.cpp337 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
369 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
370 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
383 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
384 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v6i32); in SITargetLowering()
397 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
398 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32); in SITargetLowering()
411 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
412 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32); in SITargetLowering()
425 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
[all …]
H A DAMDGPUISelDAGToDAG.cpp235 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo); in matchLoadD16FromBuildVector()
502 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); in SelectBuildVector()
660 case ISD::SCALAR_TO_VECTOR: in Select()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h656 SCALAR_TO_VECTOR, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp69 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
310 SDValue OtherVal = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, OtherVT, in ScalarizeVecRes_UnaryOpWithTwoResults()
386 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo)); in ScalarizeVecRes_OverflowOp()
875 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
889 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOpWithExtraInput()
906 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_UnaryOp_StrictFP()
985 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res); in ScalarizeVecOp_VSETCC()
1015 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_FP_ROUND()
1030 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_ROUND()
1044 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_FP_EXTEND()
[all …]
H A DSelectionDAGDumper.cpp348 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; in getOperationName()
H A DLegalizeDAG.cpp404 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
1929 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V); in ExpandBVWithShuffles()
2037 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
2092 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
2095 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
3540 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
5977 case ISD::SCALAR_TO_VECTOR: { in PromoteNode()
H A DDAGCombiner.cpp2023 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); in visit()
6251 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && in hoistLogicOpWithSameOpcodeHands()
16649 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && VT.isScalarInteger()) { in visitBITCAST()
23258 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
23602 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
23690 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
23857 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
25283 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
25317 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar); in visitCONCAT_VECTORS()
26221 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
[all …]
H A DLegalizeIntegerTypes.cpp146 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
1981 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
5505 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
H A DTargetLowering.cpp1219 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedBits()
3233 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedVectorElts()
3377 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && DemandedElts == 1) in SimplifyDemandedVectorElts()
3379 Op, TLO.DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAG.cpp3584 case ISD::SCALAR_TO_VECTOR: { in computeKnownBits()
5645 case ISD::SCALAR_TO_VECTOR: in canCreateUndefOrPoison()
6572 case ISD::SCALAR_TO_VECTOR: in getNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp257 case ISD::SCALAR_TO_VECTOR: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1191 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
1673 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
2044 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in X86TargetLowering()
2308 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32f16, Custom); in X86TargetLowering()
2362 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8f16, Legal); in X86TargetLowering()
2363 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16f16, Custom); in X86TargetLowering()
2638 ISD::SCALAR_TO_VECTOR, in X86TargetLowering()
5215 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetConstantBitsFromNode()
5988 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetShuffleAndZeroables()
6320 case ISD::SCALAR_TO_VECTOR: in getFauxShuffleMask()
[all …]
H A DX86ISelLoweringCall.cpp838 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, in LowerReturn()
1081 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, ValReturned); in lowerRegToMasks()
1436 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val) in LowerMemArgument()
2226 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); in LowerCall()
H A DX86ISelDAGToDAG.cpp1315 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1317 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
H A DX86FastISel.cpp2675 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp888 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
996 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
1001 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Custom); in PPCTargetLowering()
1002 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
1003 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
1018 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
1021 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
1025 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
1026 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp475 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
615 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in SystemZTargetLowering()
616 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in SystemZTargetLowering()
6190 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
6456 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
6480 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerVECTOR_SHUFFLE()
6695 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerShift()
7116 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp309 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in LoongArchTargetLowering()
330 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in LoongArchTargetLowering()
376 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in LoongArchTargetLowering()
397 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in LoongArchTargetLowering()
510 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1174 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR); in AArch64TargetLowering()
2323 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, PreferNEON ? Legal : Expand); in addTypeForFixedLengthSVE()
5926 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, N); in LowerINTRINSIC_WO_CHAIN()
6909 SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load); in LowerLOAD()
11426 case ISD::SCALAR_TO_VECTOR: in LowerSELECT_CC()
14002 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) in LowerVECTOR_SHUFFLE()
14967 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in LowerBUILD_VECTOR()
15259 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Op0); in LowerBUILD_VECTOR()
21236 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, Op1); in performAddSubIntoVectorOp()
21239 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, Op0); in performAddSubIntoVectorOp()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp353 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in addMVEVectorTypes()
425 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in addMVEVectorTypes()
471 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in addMVEVectorTypes()
6132 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
6134 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
8092 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
8892 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { in LowerVECTOR_SHUFFLE()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td833 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2683 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecT, SplatValue); in LowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp801 ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
929 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1110 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1275 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in RISCVTargetLowering()
1505 setOperationAction({ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR}, VT, in RISCVTargetLowering()
7373 case ISD::SCALAR_TO_VECTOR: { in LowerOperation()
7379 SDValue V = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, WideVT, Scalar); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1732 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()

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