1 /* $OpenBSD: glxsb.c,v 1.7 2007/02/12 14:31:45 tom Exp $ */
2
3 /*
4 * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org>
5 * Copyright (c) 2003, 2004 Theo de Raadt
6 * Copyright (c) 2003 Jason Wright
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Driver for the security block on the AMD Geode LX processors
23 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf
24 */
25
26 #include <sys/param.h>
27 #include <sys/systm.h>
28 #include <sys/bus.h>
29 #include <sys/errno.h>
30 #include <sys/kernel.h>
31 #include <sys/lock.h>
32 #include <sys/malloc.h>
33 #include <sys/mbuf.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/proc.h>
37 #include <sys/random.h>
38 #include <sys/rman.h>
39 #include <sys/rwlock.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
42
43 #include <machine/bus.h>
44 #include <machine/cpufunc.h>
45 #include <machine/resource.h>
46
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49
50 #include <opencrypto/cryptodev.h>
51 #include <opencrypto/xform.h>
52
53 #include "cryptodev_if.h"
54 #include "glxsb.h"
55
56 #define PCI_VENDOR_AMD 0x1022 /* AMD */
57 #define PCI_PRODUCT_AMD_GEODE_LX_CRYPTO 0x2082 /* Geode LX Crypto */
58
59 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */
60 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */
61 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */
62 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */
63 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */
64 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */
65 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */
66
67 /* For GLD_MSR_CTRL: */
68 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */
69 #define SB_GMC_DIV1 0x0001
70 #define SB_GMC_DIV2 0x0002
71 #define SB_GMC_DIV3 0x0003
72 #define SB_GMC_DIV_MASK 0x0003
73 #define SB_GMC_SBI 0x0004 /* AES swap bits */
74 #define SB_GMC_SBY 0x0008 /* AES swap bytes */
75 #define SB_GMC_TW 0x0010 /* Time write (EEPROM) */
76 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */
77 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */
78 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */
79 #define SB_GMC_T_SEL3 0x0300 /* RNG LFSR+whitener */
80 #define SB_GMC_T_SEL_MASK 0x0300
81 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */
82 #define SB_GMC_T_TM 0x0800 /* RNG test mode */
83 /* (deterministic) */
84
85 /* Security Block configuration/control registers (offsets from base) */
86 #define SB_CTL_A 0x0000 /* RW - SB Control A */
87 #define SB_CTL_B 0x0004 /* RW - SB Control B */
88 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */
89 #define SB_SOURCE_A 0x0010 /* RW - Source A */
90 #define SB_DEST_A 0x0014 /* RW - Destination A */
91 #define SB_LENGTH_A 0x0018 /* RW - Length A */
92 #define SB_SOURCE_B 0x0020 /* RW - Source B */
93 #define SB_DEST_B 0x0024 /* RW - Destination B */
94 #define SB_LENGTH_B 0x0028 /* RW - Length B */
95 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */
96 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */
97 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */
98 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */
99 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */
100 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */
101 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */
102 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */
103 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */
104 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */
105 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */
106 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */
107 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */
108 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */
109 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */
110 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */
111
112 /* For SB_CTL_A and _B */
113 #define SB_CTL_ST 0x0001 /* Start operation (enc/dec) */
114 #define SB_CTL_ENC 0x0002 /* Encrypt (0 is decrypt) */
115 #define SB_CTL_DEC 0x0000 /* Decrypt */
116 #define SB_CTL_WK 0x0004 /* Use writable key (we set) */
117 #define SB_CTL_DC 0x0008 /* Destination coherent */
118 #define SB_CTL_SC 0x0010 /* Source coherent */
119 #define SB_CTL_CBC 0x0020 /* CBC (0 is ECB) */
120
121 /* For SB_AES_INT */
122 #define SB_AI_DISABLE_AES_A 0x0001 /* Disable AES A compl int */
123 #define SB_AI_ENABLE_AES_A 0x0000 /* Enable AES A compl int */
124 #define SB_AI_DISABLE_AES_B 0x0002 /* Disable AES B compl int */
125 #define SB_AI_ENABLE_AES_B 0x0000 /* Enable AES B compl int */
126 #define SB_AI_DISABLE_EEPROM 0x0004 /* Disable EEPROM op comp int */
127 #define SB_AI_ENABLE_EEPROM 0x0000 /* Enable EEPROM op compl int */
128 #define SB_AI_AES_A_COMPLETE 0x10000 /* AES A operation complete */
129 #define SB_AI_AES_B_COMPLETE 0x20000 /* AES B operation complete */
130 #define SB_AI_EEPROM_COMPLETE 0x40000 /* EEPROM operation complete */
131
132 #define SB_AI_CLEAR_INTR \
133 (SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B |\
134 SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE |\
135 SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE)
136
137 #define SB_RNS_TRNG_VALID 0x0001 /* in SB_RANDOM_NUM_STATUS */
138
139 #define SB_MEM_SIZE 0x0810 /* Size of memory block */
140
141 #define SB_AES_ALIGN 0x0010 /* Source and dest buffers */
142 /* must be 16-byte aligned */
143 #define SB_AES_BLOCK_SIZE 0x0010
144
145 /*
146 * The Geode LX security block AES acceleration doesn't perform scatter-
147 * gather: it just takes source and destination addresses. Therefore the
148 * plain- and ciphertexts need to be contiguous. To this end, we allocate
149 * a buffer for both, and accept the overhead of copying in and out. If
150 * the number of bytes in one operation is bigger than allowed for by the
151 * buffer (buffer is twice the size of the max length, as it has both input
152 * and output) then we have to perform multiple encryptions/decryptions.
153 */
154
155 #define GLXSB_MAX_AES_LEN 16384
156
157 MALLOC_DEFINE(M_GLXSB, "glxsb_data", "Glxsb Data");
158
159 struct glxsb_dma_map {
160 bus_dmamap_t dma_map; /* DMA map */
161 bus_dma_segment_t dma_seg; /* segments */
162 int dma_nsegs; /* #segments */
163 int dma_size; /* size */
164 caddr_t dma_vaddr; /* virtual address */
165 bus_addr_t dma_paddr; /* physical address */
166 };
167
168 struct glxsb_taskop {
169 struct glxsb_session *to_ses; /* crypto session */
170 struct cryptop *to_crp; /* cryptop to perfom */
171 };
172
173 struct glxsb_softc {
174 device_t sc_dev; /* device backpointer */
175 struct resource *sc_sr; /* resource */
176 int sc_rid; /* resource rid */
177 struct callout sc_rngco; /* RNG callout */
178 int sc_rnghz; /* RNG callout ticks */
179 bus_dma_tag_t sc_dmat; /* DMA tag */
180 struct glxsb_dma_map sc_dma; /* DMA map */
181 int32_t sc_cid; /* crypto tag */
182 struct mtx sc_task_mtx; /* task mutex */
183 struct taskqueue *sc_tq; /* task queue */
184 struct task sc_cryptotask; /* task */
185 struct glxsb_taskop sc_to; /* task's crypto operation */
186 int sc_task_count; /* tasks count */
187 };
188
189 static int glxsb_probe(device_t);
190 static int glxsb_attach(device_t);
191 static int glxsb_detach(device_t);
192
193 static void glxsb_dmamap_cb(void *, bus_dma_segment_t *, int, int);
194 static int glxsb_dma_alloc(struct glxsb_softc *);
195 static void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *);
196 static void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *);
197 static void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *);
198
199 static void glxsb_rnd(void *);
200 static int glxsb_crypto_setup(struct glxsb_softc *);
201 static int glxsb_crypto_probesession(device_t,
202 const struct crypto_session_params *);
203 static int glxsb_crypto_newsession(device_t, crypto_session_t,
204 const struct crypto_session_params *);
205 static void glxsb_crypto_freesession(device_t, crypto_session_t);
206 static int glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t,
207 uint32_t, const void *, int, const void *);
208
209 static int glxsb_crypto_encdec(struct cryptop *, struct glxsb_session *,
210 struct glxsb_softc *);
211
212 static void glxsb_crypto_task(void *, int);
213 static int glxsb_crypto_process(device_t, struct cryptop *, int);
214
215 static device_method_t glxsb_methods[] = {
216 /* device interface */
217 DEVMETHOD(device_probe, glxsb_probe),
218 DEVMETHOD(device_attach, glxsb_attach),
219 DEVMETHOD(device_detach, glxsb_detach),
220
221 /* crypto device methods */
222 DEVMETHOD(cryptodev_probesession, glxsb_crypto_probesession),
223 DEVMETHOD(cryptodev_newsession, glxsb_crypto_newsession),
224 DEVMETHOD(cryptodev_freesession, glxsb_crypto_freesession),
225 DEVMETHOD(cryptodev_process, glxsb_crypto_process),
226
227 {0,0}
228 };
229
230 static driver_t glxsb_driver = {
231 "glxsb",
232 glxsb_methods,
233 sizeof(struct glxsb_softc)
234 };
235
236 DRIVER_MODULE(glxsb, pci, glxsb_driver, 0, 0);
237 MODULE_VERSION(glxsb, 1);
238 MODULE_DEPEND(glxsb, crypto, 1, 1, 1);
239
240 static int
glxsb_probe(device_t dev)241 glxsb_probe(device_t dev)
242 {
243
244 if (pci_get_vendor(dev) == PCI_VENDOR_AMD &&
245 pci_get_device(dev) == PCI_PRODUCT_AMD_GEODE_LX_CRYPTO) {
246 device_set_desc(dev,
247 "AMD Geode LX Security Block (AES-128-CBC, RNG)");
248 return (BUS_PROBE_DEFAULT);
249 }
250
251 return (ENXIO);
252 }
253
254 static int
glxsb_attach(device_t dev)255 glxsb_attach(device_t dev)
256 {
257 struct glxsb_softc *sc = device_get_softc(dev);
258 uint64_t msr;
259
260 sc->sc_dev = dev;
261 msr = rdmsr(SB_GLD_MSR_CAP);
262
263 if ((msr & 0xFFFF00) != 0x130400) {
264 device_printf(dev, "unknown ID 0x%x\n",
265 (int)((msr & 0xFFFF00) >> 16));
266 return (ENXIO);
267 }
268
269 pci_enable_busmaster(dev);
270
271 /* Map in the security block configuration/control registers */
272 sc->sc_rid = PCIR_BAR(0);
273 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
274 RF_ACTIVE);
275 if (sc->sc_sr == NULL) {
276 device_printf(dev, "cannot map register space\n");
277 return (ENXIO);
278 }
279
280 /*
281 * Configure the Security Block.
282 *
283 * We want to enable the noise generator (T_NE), and enable the
284 * linear feedback shift register and whitener post-processing
285 * (T_SEL = 3). Also ensure that test mode (deterministic values)
286 * is disabled.
287 */
288 msr = rdmsr(SB_GLD_MSR_CTRL);
289 msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK);
290 msr |= SB_GMC_T_NE | SB_GMC_T_SEL3;
291 #if 0
292 msr |= SB_GMC_SBI | SB_GMC_SBY; /* for AES, if necessary */
293 #endif
294 wrmsr(SB_GLD_MSR_CTRL, msr);
295
296 /* Disable interrupts */
297 bus_write_4(sc->sc_sr, SB_AES_INT, SB_AI_CLEAR_INTR);
298
299 /* Allocate a contiguous DMA-able buffer to work in */
300 if (glxsb_dma_alloc(sc) != 0)
301 goto fail0;
302
303 /* Initialize our task queue */
304 sc->sc_tq = taskqueue_create("glxsb_taskq", M_NOWAIT | M_ZERO,
305 taskqueue_thread_enqueue, &sc->sc_tq);
306 if (sc->sc_tq == NULL) {
307 device_printf(dev, "cannot create task queue\n");
308 goto fail0;
309 }
310 if (taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
311 device_get_nameunit(dev)) != 0) {
312 device_printf(dev, "cannot start task queue\n");
313 goto fail1;
314 }
315 TASK_INIT(&sc->sc_cryptotask, 0, glxsb_crypto_task, sc);
316
317 /* Initialize crypto */
318 if (glxsb_crypto_setup(sc) != 0)
319 goto fail1;
320
321 /* Install a periodic collector for the "true" (AMD's word) RNG */
322 if (hz > 100)
323 sc->sc_rnghz = hz / 100;
324 else
325 sc->sc_rnghz = 1;
326 callout_init(&sc->sc_rngco, 1);
327 glxsb_rnd(sc);
328
329 return (0);
330
331 fail1:
332 taskqueue_free(sc->sc_tq);
333 fail0:
334 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr);
335 return (ENXIO);
336 }
337
338 static int
glxsb_detach(device_t dev)339 glxsb_detach(device_t dev)
340 {
341 struct glxsb_softc *sc = device_get_softc(dev);
342
343 crypto_unregister_all(sc->sc_cid);
344
345 callout_drain(&sc->sc_rngco);
346 taskqueue_drain(sc->sc_tq, &sc->sc_cryptotask);
347 bus_generic_detach(dev);
348 glxsb_dma_free(sc, &sc->sc_dma);
349 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr);
350 taskqueue_free(sc->sc_tq);
351 mtx_destroy(&sc->sc_task_mtx);
352 return (0);
353 }
354
355 /*
356 * callback for bus_dmamap_load()
357 */
358 static void
glxsb_dmamap_cb(void * arg,bus_dma_segment_t * seg,int nseg,int error)359 glxsb_dmamap_cb(void *arg, bus_dma_segment_t *seg, int nseg, int error)
360 {
361
362 bus_addr_t *paddr = (bus_addr_t*) arg;
363 *paddr = seg[0].ds_addr;
364 }
365
366 static int
glxsb_dma_alloc(struct glxsb_softc * sc)367 glxsb_dma_alloc(struct glxsb_softc *sc)
368 {
369 struct glxsb_dma_map *dma = &sc->sc_dma;
370 int rc;
371
372 dma->dma_nsegs = 1;
373 dma->dma_size = GLXSB_MAX_AES_LEN * 2;
374
375 /* Setup DMA descriptor area */
376 rc = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
377 SB_AES_ALIGN, 0, /* alignments, bounds */
378 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
379 BUS_SPACE_MAXADDR, /* highaddr */
380 NULL, NULL, /* filter, filterarg */
381 dma->dma_size, /* maxsize */
382 dma->dma_nsegs, /* nsegments */
383 dma->dma_size, /* maxsegsize */
384 BUS_DMA_ALLOCNOW, /* flags */
385 NULL, NULL, /* lockfunc, lockarg */
386 &sc->sc_dmat);
387 if (rc != 0) {
388 device_printf(sc->sc_dev,
389 "cannot allocate DMA tag (%d)\n", rc);
390 return (rc);
391 }
392
393 rc = bus_dmamem_alloc(sc->sc_dmat, (void **)&dma->dma_vaddr,
394 BUS_DMA_NOWAIT, &dma->dma_map);
395 if (rc != 0) {
396 device_printf(sc->sc_dev,
397 "cannot allocate DMA memory of %d bytes (%d)\n",
398 dma->dma_size, rc);
399 goto fail0;
400 }
401
402 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr,
403 dma->dma_size, glxsb_dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
404 if (rc != 0) {
405 device_printf(sc->sc_dev,
406 "cannot load DMA memory for %d bytes (%d)\n",
407 dma->dma_size, rc);
408 goto fail1;
409 }
410
411 return (0);
412
413 fail1:
414 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map);
415 fail0:
416 bus_dma_tag_destroy(sc->sc_dmat);
417 return (rc);
418 }
419
420 static void
glxsb_dma_pre_op(struct glxsb_softc * sc,struct glxsb_dma_map * dma)421 glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma)
422 {
423
424 bus_dmamap_sync(sc->sc_dmat, dma->dma_map,
425 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
426 }
427
428 static void
glxsb_dma_post_op(struct glxsb_softc * sc,struct glxsb_dma_map * dma)429 glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma)
430 {
431
432 bus_dmamap_sync(sc->sc_dmat, dma->dma_map,
433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
434 }
435
436 static void
glxsb_dma_free(struct glxsb_softc * sc,struct glxsb_dma_map * dma)437 glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma)
438 {
439
440 bus_dmamap_unload(sc->sc_dmat, dma->dma_map);
441 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map);
442 bus_dma_tag_destroy(sc->sc_dmat);
443 }
444
445 static void
glxsb_rnd(void * v)446 glxsb_rnd(void *v)
447 {
448 struct glxsb_softc *sc = v;
449 uint32_t status, value;
450
451 status = bus_read_4(sc->sc_sr, SB_RANDOM_NUM_STATUS);
452 if (status & SB_RNS_TRNG_VALID) {
453 value = bus_read_4(sc->sc_sr, SB_RANDOM_NUM);
454 /* feed with one uint32 */
455 /* MarkM: FIX!! Check that this does not swamp the harvester! */
456 random_harvest_queue(&value, sizeof(value), RANDOM_PURE_GLXSB);
457 }
458
459 callout_reset(&sc->sc_rngco, sc->sc_rnghz, glxsb_rnd, sc);
460 }
461
462 static int
glxsb_crypto_setup(struct glxsb_softc * sc)463 glxsb_crypto_setup(struct glxsb_softc *sc)
464 {
465
466 sc->sc_cid = crypto_get_driverid(sc->sc_dev,
467 sizeof(struct glxsb_session), CRYPTOCAP_F_HARDWARE);
468
469 if (sc->sc_cid < 0) {
470 device_printf(sc->sc_dev, "cannot get crypto driver id\n");
471 return (ENOMEM);
472 }
473
474 mtx_init(&sc->sc_task_mtx, "glxsb_crypto_mtx", NULL, MTX_DEF);
475
476 return (0);
477 }
478
479 static int
glxsb_crypto_probesession(device_t dev,const struct crypto_session_params * csp)480 glxsb_crypto_probesession(device_t dev, const struct crypto_session_params *csp)
481 {
482
483 if (csp->csp_flags != 0)
484 return (EINVAL);
485
486 /*
487 * We only support HMAC algorithms to be able to work with
488 * ipsec(4), so if we are asked only for authentication without
489 * encryption, don't pretend we can accelerate it.
490 */
491 switch (csp->csp_mode) {
492 case CSP_MODE_ETA:
493 switch (csp->csp_auth_alg) {
494 case CRYPTO_NULL_HMAC:
495 case CRYPTO_SHA1_HMAC:
496 case CRYPTO_RIPEMD160_HMAC:
497 case CRYPTO_SHA2_256_HMAC:
498 case CRYPTO_SHA2_384_HMAC:
499 case CRYPTO_SHA2_512_HMAC:
500 break;
501 default:
502 return (EINVAL);
503 }
504 /* FALLTHROUGH */
505 case CSP_MODE_CIPHER:
506 switch (csp->csp_cipher_alg) {
507 case CRYPTO_AES_CBC:
508 if (csp->csp_cipher_klen * 8 != 128)
509 return (EINVAL);
510 break;
511 default:
512 return (EINVAL);
513 }
514 default:
515 return (EINVAL);
516 }
517 return (CRYPTODEV_PROBE_HARDWARE);
518 }
519
520 static int
glxsb_crypto_newsession(device_t dev,crypto_session_t cses,const struct crypto_session_params * csp)521 glxsb_crypto_newsession(device_t dev, crypto_session_t cses,
522 const struct crypto_session_params *csp)
523 {
524 struct glxsb_softc *sc = device_get_softc(dev);
525 struct glxsb_session *ses;
526 int error;
527
528 ses = crypto_get_driver_session(cses);
529
530 /* Copy the key (Geode LX wants the primary key only) */
531 if (csp->csp_cipher_key != NULL)
532 bcopy(csp->csp_cipher_key, ses->ses_key, sizeof(ses->ses_key));
533
534 if (csp->csp_auth_alg != 0) {
535 error = glxsb_hash_setup(ses, csp);
536 if (error != 0) {
537 glxsb_crypto_freesession(sc->sc_dev, cses);
538 return (error);
539 }
540 }
541
542 return (0);
543 }
544
545 static void
glxsb_crypto_freesession(device_t dev,crypto_session_t cses)546 glxsb_crypto_freesession(device_t dev, crypto_session_t cses)
547 {
548 struct glxsb_session *ses;
549
550 ses = crypto_get_driver_session(cses);
551 glxsb_hash_free(ses);
552 }
553
554 static int
glxsb_aes(struct glxsb_softc * sc,uint32_t control,uint32_t psrc,uint32_t pdst,const void * key,int len,const void * iv)555 glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc,
556 uint32_t pdst, const void *key, int len, const void *iv)
557 {
558 uint32_t status;
559 int i;
560
561 if (len & 0xF) {
562 device_printf(sc->sc_dev,
563 "len must be a multiple of 16 (not %d)\n", len);
564 return (EINVAL);
565 }
566
567 /* Set the source */
568 bus_write_4(sc->sc_sr, SB_SOURCE_A, psrc);
569
570 /* Set the destination address */
571 bus_write_4(sc->sc_sr, SB_DEST_A, pdst);
572
573 /* Set the data length */
574 bus_write_4(sc->sc_sr, SB_LENGTH_A, len);
575
576 /* Set the IV */
577 if (iv != NULL) {
578 bus_write_region_4(sc->sc_sr, SB_CBC_IV, iv, 4);
579 control |= SB_CTL_CBC;
580 }
581
582 /* Set the key */
583 bus_write_region_4(sc->sc_sr, SB_WKEY, key, 4);
584
585 /* Ask the security block to do it */
586 bus_write_4(sc->sc_sr, SB_CTL_A,
587 control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST);
588
589 /*
590 * Now wait until it is done.
591 *
592 * We do a busy wait. Obviously the number of iterations of
593 * the loop required to perform the AES operation depends upon
594 * the number of bytes to process.
595 *
596 * On a 500 MHz Geode LX we see
597 *
598 * length (bytes) typical max iterations
599 * 16 12
600 * 64 22
601 * 256 59
602 * 1024 212
603 * 8192 1,537
604 *
605 * Since we have a maximum size of operation defined in
606 * GLXSB_MAX_AES_LEN, we use this constant to decide how long
607 * to wait. Allow an order of magnitude longer than it should
608 * really take, just in case.
609 */
610
611 for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) {
612 status = bus_read_4(sc->sc_sr, SB_CTL_A);
613 if ((status & SB_CTL_ST) == 0) /* Done */
614 return (0);
615 }
616
617 device_printf(sc->sc_dev, "operation failed to complete\n");
618 return (EIO);
619 }
620
621 static int
glxsb_crypto_encdec(struct cryptop * crp,struct glxsb_session * ses,struct glxsb_softc * sc)622 glxsb_crypto_encdec(struct cryptop *crp, struct glxsb_session *ses,
623 struct glxsb_softc *sc)
624 {
625 char *op_src, *op_dst;
626 const void *key;
627 uint32_t op_psrc, op_pdst;
628 uint8_t op_iv[SB_AES_BLOCK_SIZE];
629 int error;
630 int len, tlen, xlen;
631 int offset;
632 uint32_t control;
633
634 if ((crp->crp_payload_length % SB_AES_BLOCK_SIZE) != 0)
635 return (EINVAL);
636
637 /* How much of our buffer will we need to use? */
638 xlen = crp->crp_payload_length > GLXSB_MAX_AES_LEN ?
639 GLXSB_MAX_AES_LEN : crp->crp_payload_length;
640
641 /*
642 * XXX Check if we can have input == output on Geode LX.
643 * XXX In the meantime, use two separate (adjacent) buffers.
644 */
645 op_src = sc->sc_dma.dma_vaddr;
646 op_dst = (char *)sc->sc_dma.dma_vaddr + xlen;
647
648 op_psrc = sc->sc_dma.dma_paddr;
649 op_pdst = sc->sc_dma.dma_paddr + xlen;
650
651 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
652 control = SB_CTL_ENC;
653 else
654 control = SB_CTL_DEC;
655
656 crypto_read_iv(crp, op_iv);
657
658 offset = 0;
659 tlen = crp->crp_payload_length;
660
661 if (crp->crp_cipher_key != NULL)
662 key = crp->crp_cipher_key;
663 else
664 key = ses->ses_key;
665
666 /* Process the data in GLXSB_MAX_AES_LEN chunks */
667 while (tlen > 0) {
668 len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen;
669 crypto_copydata(crp, crp->crp_payload_start + offset, len,
670 op_src);
671
672 glxsb_dma_pre_op(sc, &sc->sc_dma);
673
674 error = glxsb_aes(sc, control, op_psrc, op_pdst, key, len,
675 op_iv);
676
677 glxsb_dma_post_op(sc, &sc->sc_dma);
678 if (error != 0)
679 return (error);
680
681 crypto_copyback(crp, crp->crp_payload_start + offset, len,
682 op_dst);
683
684 offset += len;
685 tlen -= len;
686
687 /*
688 * Copy out last block for use as next iteration IV.
689 */
690 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
691 bcopy(op_dst + len - sizeof(op_iv), op_iv,
692 sizeof(op_iv));
693 else
694 bcopy(op_src + len - sizeof(op_iv), op_iv,
695 sizeof(op_iv));
696 } /* while */
697
698 /* All AES processing has now been done. */
699 bzero(sc->sc_dma.dma_vaddr, xlen * 2);
700
701 return (0);
702 }
703
704 static void
glxsb_crypto_task(void * arg,int pending)705 glxsb_crypto_task(void *arg, int pending)
706 {
707 struct glxsb_softc *sc = arg;
708 const struct crypto_session_params *csp;
709 struct glxsb_session *ses;
710 struct cryptop *crp;
711 int error;
712
713 crp = sc->sc_to.to_crp;
714 ses = sc->sc_to.to_ses;
715 csp = crypto_get_params(crp->crp_session);
716
717 /* Perform data authentication if requested before encryption */
718 if (csp->csp_mode == CSP_MODE_ETA &&
719 !CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) {
720 error = glxsb_hash_process(ses, csp, crp);
721 if (error != 0)
722 goto out;
723 }
724
725 error = glxsb_crypto_encdec(crp, ses, sc);
726 if (error != 0)
727 goto out;
728
729 /* Perform data authentication if requested after encryption */
730 if (csp->csp_mode == CSP_MODE_ETA &&
731 CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) {
732 error = glxsb_hash_process(ses, csp, crp);
733 if (error != 0)
734 goto out;
735 }
736 out:
737 mtx_lock(&sc->sc_task_mtx);
738 sc->sc_task_count--;
739 mtx_unlock(&sc->sc_task_mtx);
740
741 crp->crp_etype = error;
742 crypto_unblock(sc->sc_cid, CRYPTO_SYMQ);
743 crypto_done(crp);
744 }
745
746 static int
glxsb_crypto_process(device_t dev,struct cryptop * crp,int hint)747 glxsb_crypto_process(device_t dev, struct cryptop *crp, int hint)
748 {
749 struct glxsb_softc *sc = device_get_softc(dev);
750 struct glxsb_session *ses;
751
752 ses = crypto_get_driver_session(crp->crp_session);
753
754 mtx_lock(&sc->sc_task_mtx);
755 if (sc->sc_task_count != 0) {
756 mtx_unlock(&sc->sc_task_mtx);
757 return (ERESTART);
758 }
759 sc->sc_task_count++;
760
761 sc->sc_to.to_crp = crp;
762 sc->sc_to.to_ses = ses;
763 mtx_unlock(&sc->sc_task_mtx);
764
765 taskqueue_enqueue(sc->sc_tq, &sc->sc_cryptotask);
766 return(0);
767 }
768