1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 /*******************************************************************************/ 24 /*! \file sa.h 25 * \brief The file defines the constants, data structure, and functions defined by LL API 26 */ 27 /******************************************************************************/ 28 29 #ifndef __SA_H__ 30 #define __SA_H__ 31 32 #include <dev/pms/RefTisa/sallsdk/api/sa_spec.h> 33 #include <dev/pms/RefTisa/sallsdk/api/sa_err.h> 34 35 /* TestBase needed to have the 'Multi-Data fetch disable' feature */ 36 #define SA_CONFIG_MDFD_REGISTRY 37 38 #define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ 39 (bitptr)&(((STRUCT_TYPE *)0)->FEILD) 40 41 #if defined(SA_CPU_LITTLE_ENDIAN) 42 43 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 44 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 45 46 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 47 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 48 49 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 50 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 51 52 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 53 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 54 55 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 56 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); 58 59 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 60 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); 64 65 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 66 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 67 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 68 69 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 70 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 71 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 72 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 73 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 74 75 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 76 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 77 78 79 #elif defined(SA_CPU_BIG_ENDIAN) 80 81 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 82 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); 84 85 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 86 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); 90 91 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 92 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 93 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 94 95 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 96 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 97 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 98 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 99 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 100 101 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 102 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 103 104 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 105 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 106 107 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 108 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 109 110 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 111 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 112 113 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 114 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 115 116 #else 117 118 #error (Host CPU endianess undefined!!) 119 120 #endif 121 122 #define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \ 123 OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \ 124 OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \ 125 OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \ 126 OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved); 127 128 129 /************************************************************************** 130 * define byte swap macro * 131 **************************************************************************/ 132 /*! \def AGSA_FLIP_2_BYTES(_x) 133 * \brief AGSA_FLIP_2_BYTES macro 134 * 135 * use to flip two bytes 136 */ 137 #define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \ 138 ((((bit16)(_x))&0xFF00)>>8))) 139 140 /*! \def AGSA_FLIP_4_BYTES(_x) 141 * \brief AGSA_FLIP_4_BYTES macro 142 * 143 * use to flip four bytes 144 */ 145 #define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \ 146 ((((bit32)(_x))&0x0000FF00)<<8)| \ 147 ((((bit32)(_x))&0x00FF0000)>>8)| \ 148 ((((bit32)(_x))&0xFF000000)>>24))) 149 150 151 #if defined(SA_CPU_LITTLE_ENDIAN) 152 153 /*! \def LEBIT16_TO_BIT16(_x) 154 * \brief LEBIT16_TO_BIT16 macro 155 * 156 * use to convert little endian bit16 to host bit16 157 */ 158 #ifndef LEBIT16_TO_BIT16 159 #define LEBIT16_TO_BIT16(_x) (_x) 160 #endif 161 162 /*! \def BIT16_TO_LEBIT16(_x) 163 * \brief BIT16_TO_LEBIT16 macro 164 * 165 * use to convert host bit16 to little endian bit16 166 */ 167 #ifndef BIT16_TO_LEBIT16 168 #define BIT16_TO_LEBIT16(_x) (_x) 169 #endif 170 171 /*! \def BEBIT16_TO_BIT16(_x) 172 * \brief BEBIT16_TO_BIT16 macro 173 * 174 * use to convert big endian bit16 to host bit16 175 */ 176 #ifndef BEBIT16_TO_BIT16 177 #define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 178 #endif 179 180 /*! \def BIT16_TO_BEBIT16(_x) 181 * \brief BIT16_TO_BEBIT16 macro 182 * 183 * use to convert host bit16 to big endian bit16 184 */ 185 #ifndef BIT16_TO_BEBIT16 186 #define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 187 #endif 188 189 /*! \def LEBIT32_TO_BIT32(_x) 190 * \brief LEBIT32_TO_BIT32 macro 191 * 192 * use to convert little endian bit32 to host bit32 193 */ 194 #ifndef LEBIT32_TO_BIT32 195 #define LEBIT32_TO_BIT32(_x) (_x) 196 #endif 197 198 /*! \def BIT32_TO_LEBIT32(_x) 199 * \brief BIT32_TO_LEBIT32 macro 200 * 201 * use to convert host bit32 to little endian bit32 202 */ 203 #ifndef BIT32_TO_LEBIT32 204 #define BIT32_TO_LEBIT32(_x) (_x) 205 #endif 206 207 /*! \def BEBIT32_TO_BIT32(_x) 208 * \brief BEBIT32_TO_BIT32 macro 209 * 210 * use to convert big endian bit32 to host bit32 211 */ 212 #ifndef BEBIT32_TO_BIT32 213 #define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 214 #endif 215 216 /*! \def BIT32_TO_BEBIT32(_x) 217 * \brief BIT32_TO_BEBIT32 macro 218 * 219 * use to convert host bit32 to big endian bit32 220 */ 221 #ifndef BIT32_TO_BEBIT32 222 #define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 223 #endif 224 225 226 /* 227 * bit8 to Byte[x] of bit32 228 */ 229 #ifndef BIT8_TO_BIT32_B0 230 #define BIT8_TO_BIT32_B0(_x) ((bit32)(_x)) 231 #endif 232 233 #ifndef BIT8_TO_BIT32_B1 234 #define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8) 235 #endif 236 237 #ifndef BIT8_TO_BIT32_B2 238 #define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16) 239 #endif 240 241 #ifndef BIT8_TO_BIT32_B3 242 #define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24) 243 #endif 244 245 /* 246 * Byte[x] of bit32 to bit8 247 */ 248 #ifndef BIT32_B0_TO_BIT8 249 #define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 250 #endif 251 252 #ifndef BIT32_B1_TO_BIT8 253 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 254 #endif 255 256 #ifndef BIT32_B2_TO_BIT8 257 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 258 #endif 259 260 #ifndef BIT32_B3_TO_BIT8 261 #define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 262 #endif 263 264 #elif defined(SA_CPU_BIG_ENDIAN) 265 266 /*! \def LEBIT16_TO_BIT16(_x) 267 * \brief LEBIT16_TO_BIT16 macro 268 * 269 * use to convert little endian bit16 to host bit16 270 */ 271 #ifndef LEBIT16_TO_BIT16 272 #define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 273 #endif 274 275 /*! \def BIT16_TO_LEBIT16(_x) 276 * \brief BIT16_TO_LEBIT16 macro 277 * 278 * use to convert host bit16 to little endian bit16 279 */ 280 #ifndef BIT16_TO_LEBIT16 281 #define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 282 #endif 283 284 /*! \def BEBIT16_TO_BIT16(_x) 285 * \brief BEBIT16_TO_BIT16 macro 286 * 287 * use to convert big endian bit16 to host bit16 288 */ 289 #ifndef BEBIT16_TO_BIT16 290 #define BEBIT16_TO_BIT16(_x) (_x) 291 #endif 292 293 /*! \def BIT16_TO_BEBIT16(_x) 294 * \brief BIT16_TO_BEBIT16 macro 295 * 296 * use to convert host bit16 to big endian bit16 297 */ 298 #ifndef BIT16_TO_BEBIT16 299 #define BIT16_TO_BEBIT16(_x) (_x) 300 #endif 301 302 /*! \def LEBIT32_TO_BIT32(_x) 303 * \brief LEBIT32_TO_BIT32 macro 304 * 305 * use to convert little endian bit32 to host bit32 306 */ 307 #ifndef LEBIT32_TO_BIT32 308 #define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 309 #endif 310 311 /*! \def BIT32_TO_LEBIT32(_x) 312 * \brief BIT32_TO_LEBIT32 macro 313 * 314 * use to convert host bit32 to little endian bit32 315 */ 316 #ifndef BIT32_TO_LEBIT32 317 #define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 318 #endif 319 320 /*! \def BEBIT32_TO_BIT32(_x) 321 * \brief BEBIT32_TO_BIT32 macro 322 * 323 * use to convert big endian bit32 to host bit32 324 */ 325 #ifndef BEBIT32_TO_BIT32 326 #define BEBIT32_TO_BIT32(_x) (_x) 327 #endif 328 329 /*! \def BIT32_TO_BEBIT32(_x) 330 * \brief BIT32_TO_BEBIT32 macro 331 * 332 * use to convert host bit32 to big endian bit32 333 */ 334 #ifndef BIT32_TO_BEBIT32 335 #define BIT32_TO_BEBIT32(_x) (_x) 336 #endif 337 338 339 /* 340 * bit8 to Byte[x] of bit32 341 */ 342 #ifndef BIT8_TO_BIT32_B0 343 #define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24) 344 #endif 345 346 #ifndef BIT8_TO_BIT32_B1 347 #define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16) 348 #endif 349 350 #ifndef BIT8_TO_BIT32_B2 351 #define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8) 352 #endif 353 354 #ifndef BIT8_TO_BIT32_B3 355 #define BIT8_TO_BIT32_B3(_x) ((bit32)(_x)) 356 #endif 357 358 /* 359 * Byte[x] of bit32 to bit8 360 */ 361 #ifndef BIT32_B0_TO_BIT8 362 #define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 363 #endif 364 365 #ifndef BIT32_B1_TO_BIT8 366 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 367 #endif 368 369 #ifndef BIT32_B2_TO_BIT8 370 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 371 #endif 372 373 #ifndef BIT32_B3_TO_BIT8 374 #define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 375 #endif 376 377 #else 378 379 #error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN 380 381 #endif 382 383 384 #if defined(SA_DMA_LITTLE_ENDIAN) 385 386 /* 387 * ** bit32 to bit32 388 * */ 389 #ifndef DMA_BIT32_TO_BIT32 390 #define DMA_BIT32_TO_BIT32(_x) (_x) 391 #endif 392 393 #ifndef DMA_LEBIT32_TO_BIT32 394 #define DMA_LEBIT32_TO_BIT32(_x) (_x) 395 #endif 396 397 #ifndef DMA_BEBIT32_TO_BIT32 398 #define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 399 #endif 400 401 #ifndef BIT32_TO_DMA_BIT32 402 #define BIT32_TO_DMA_BIT32(_x) (_x) 403 #endif 404 405 #ifndef BIT32_TO_DMA_LEBIT32 406 #define BIT32_TO_DMA_LEBIT32(_x) (_x) 407 #endif 408 409 #ifndef BIT32_TO_DMA_BEBIT32 410 #define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 411 #endif 412 413 414 /* 415 * ** bit16 to bit16 416 * */ 417 #ifndef DMA_BIT16_TO_BIT16 418 #define DMA_BIT16_TO_BIT16(_x) (_x) 419 #endif 420 421 #ifndef DMA_LEBIT16_TO_BIT16 422 #define DMA_LEBIT16_TO_BIT16(_x) (_x) 423 #endif 424 425 #ifndef DMA_BEBIT16_TO_BIT16 426 #define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 427 #endif 428 429 #ifndef BIT16_TO_DMA_BIT16 430 #define BIT16_TO_DMA_BIT16(_x) (_x) 431 #endif 432 433 #ifndef BIT16_TO_DMA_LEBIT16 434 #define BIT16_TO_DMA_LEBIT16(_x) (_x) 435 #endif 436 437 #ifndef BIT16_TO_DMA_BEBIT16 438 #define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 439 #endif 440 441 #if defined(SA_CPU_LITTLE_ENDIAN) 442 443 #ifndef BEBIT32_TO_DMA_BEBIT32 444 #define BEBIT32_TO_DMA_BEBIT32(_x) (_x) 445 #endif 446 447 #ifndef LEBIT32_TO_DMA_LEBIT32 448 #define LEBIT32_TO_DMA_LEBIT32(_x) (_x) 449 #endif 450 451 #ifndef DMA_LEBIT32_TO_LEBIT32 452 #define DMA_LEBIT32_TO_LEBIT32(_x) (_x) 453 #endif 454 455 #ifndef DMA_BEBIT32_TO_BEBIT32 456 #define DMA_BEBIT32_TO_BEBIT32(_x) (_x) 457 #endif 458 459 /* 460 * ** bit16 to bit16 461 * */ 462 #ifndef BEBIT16_TO_DMA_BEBIT16 463 #define BEBIT16_TO_DMA_BEBIT16(_x) (_x) 464 #endif 465 466 #ifndef LEBIT16_TO_DMA_LEBIT16 467 #define LEBIT16_TO_DMA_LEBIT16(_x) (_x) 468 #endif 469 470 #ifndef DMA_LEBIT16_TO_LEBIT16 471 #define DMA_LEBIT16_TO_LEBIT16(_x) (_x) 472 #endif 473 474 #ifndef DMA_BEBIT16_TO_BEBIT16 475 #define DMA_BEBIT16_TO_BEBIT16(_x) (_x) 476 #endif 477 478 #else /* defined(SA_CPU_BIG_ENDIAN) */ 479 480 481 /* 482 * ** bit32 to bit32 483 * */ 484 #ifndef BEBIT32_TO_DMA_BEBIT32 485 #define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 486 #endif 487 488 #ifndef LEBIT32_TO_DMA_LEBIT32 489 #define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 490 #endif 491 492 #ifndef DMA_LEBIT32_TO_LEBIT32 493 #define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 494 #endif 495 496 #ifndef DMA_BEBIT32_TO_BEBIT32 497 #define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 498 #endif 499 500 /* 501 * ** bit16 to bit16 502 * */ 503 #ifndef BEBIT16_TO_DMA_BEBIT16 504 #define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 505 #endif 506 507 #ifndef LEBIT16_TO_DMA_LEBIT16 508 #define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 509 #endif 510 511 #ifndef DMA_LEBIT16_TO_LEBIT16 512 #define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 513 #endif 514 515 #ifndef DMA_BEBIT16_TO_BEBIT16 516 #define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 517 #endif 518 519 #endif 520 521 /* 522 * bit8 to Byte[x] of bit32 523 */ 524 #ifndef BIT8_TO_DMA_BIT32_B0 525 #define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x)) 526 #endif 527 528 #ifndef BIT8_TO_DMA_BIT32_B1 529 #define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8) 530 #endif 531 532 #ifndef BIT8_TO_DMA_BIT32_B2 533 #define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16) 534 #endif 535 536 #ifndef BIT8_TO_DMA_BIT32_B3 537 #define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24) 538 #endif 539 540 /* 541 * Byte[x] of bit32 to bit8 542 */ 543 #ifndef DMA_BIT32_B0_TO_BIT8 544 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 545 #endif 546 547 #ifndef DMA_BIT32_B1_TO_BIT8 548 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 549 #endif 550 551 #ifndef DMA_BIT32_B2_TO_BIT8 552 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 553 #endif 554 555 #ifndef DMA_BIT32_B3_TO_BIT8 556 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 557 #endif 558 559 /*| | 560 | end of DMA access macros for LITTLE ENDIAN | 561 --------------------------------------------------------------------- 562 */ 563 564 #elif defined(SA_DMA_BIG_ENDIAN) /* DMA big endian */ 565 566 /*-------------------------------------------------------------------- 567 | DMA buffer access macros for BIG ENDIAN | 568 | | 569 */ 570 571 /* bit32 to bit32 */ 572 #ifndef DMA_BEBIT32_TO_BIT32 573 #define DMA_BEBIT32_TO_BIT32(_x) (_x) 574 #endif 575 576 #ifndef DMA_LEBIT32_TO_BIT32 577 #define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 578 #endif 579 580 #ifndef BIT32_TO_DMA_BIT32 581 #define BIT32_TO_DMA_BIT32(_x) (_x) 582 #endif 583 584 #ifndef BIT32_TO_DMA_LEBIT32 585 #define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 586 #endif 587 588 #ifndef BIT32_TO_DMA_BEBIT32 589 #define BIT32_TO_DMA_BEBIT32(_x) (_x) 590 #endif 591 592 /* bit16 to bit16 */ 593 #ifndef DMA_BEBIT16_TO_BIT16 594 #define DMA_BEBIT16_TO_BIT16(_x) (_x) 595 #endif 596 597 #ifndef DMA_LEBIT16_TO_BIT16 598 #define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 599 #endif 600 601 #ifndef BIT16_TO_DMA_BIT16 602 #define BIT16_TO_DMA_BIT16(_x) (_x) 603 #endif 604 605 #ifndef BIT16_TO_DMA_LEBIT16 606 #define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 607 #endif 608 609 #ifndef BIT16_TO_DMA_BEBIT16 610 #define BIT16_TO_DMA_BEBIT16(_x) (_x) 611 #endif 612 613 614 #if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */ 615 616 /* bit32 to bit32 */ 617 #ifndef BEBIT32_TO_DMA_BEBIT32 618 #define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 619 #endif 620 621 #ifndef LEBIT32_TO_DMA_LEBIT32 622 #define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 623 #endif 624 625 #ifndef DMA_LEBIT32_TO_LEBIT32 626 #define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 627 #endif 628 629 #ifndef DMA_BEBIT32_TO_BEBIT32 630 #define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 631 #endif 632 633 /* bit16 to bit16 */ 634 #ifndef BEBIT16_TO_DMA_BEBIT16 635 #define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 636 #endif 637 638 #ifndef LEBIT16_TO_DMA_LEBIT16 639 #define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 640 #endif 641 642 #ifndef DMA_LEBIT16_TO_LEBIT16 643 #define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 644 #endif 645 646 #ifndef DMA_BEBIT16_TO_BEBIT16 647 #define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 648 #endif 649 650 651 #else /* defined(SA_CPU_BIG_ENDIAN) */ 652 653 /* bit32 to bit32 */ 654 #ifndef BEBIT32_TO_DMA_BEBIT32 655 #define BEBIT32_TO_DMA_BEBIT32(_x) (_x) 656 #endif 657 658 #ifndef LEBIT32_TO_DMA_LEBIT32 659 #define LEBIT32_TO_DMA_LEBIT32(_x) (_x) 660 #endif 661 662 #ifndef DMA_LEBIT32_TO_LEBIT32 663 #define DMA_LEBIT32_TO_LEBIT32(_x) (_x) 664 #endif 665 666 #ifndef DMA_BEBIT32_TO_BEBIT32 667 #define DMA_BEBIT32_TO_BEBIT32(_x) (_x) 668 #endif 669 670 /* bit16 to bit16 */ 671 #ifndef BEBIT16_TO_DMA_BEBIT16 672 #define BEBIT16_TO_DMA_BEBIT16(_x) (_x) 673 #endif 674 675 #ifndef LEBIT16_TO_DMA_LEBIT16 676 #define LEBIT16_TO_DMA_LEBIT16(_x) (_x) 677 #endif 678 679 #ifndef DMA_LEBIT16_TO_LEBIT16 680 #define DMA_LEBIT16_TO_LEBIT16(_x) (_x) 681 #endif 682 683 #ifndef DMA_BEBIT16_TO_BEBIT16 684 #define DMA_BEBIT16_TO_BEBIT16(_x) (_x) 685 #endif 686 687 #endif 688 689 /* 690 * bit8 to Byte[x] of bit32 691 */ 692 #ifndef BIT8_TO_DMA_BIT32_B0 693 #define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24) 694 #endif 695 696 #ifndef BIT8_TO_DMA_BIT32_B1 697 #define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16) 698 #endif 699 700 #ifndef BIT8_TO_DMA_BIT32_B2 701 #define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8) 702 #endif 703 704 #ifndef BIT8_TO_DMA_BIT32_B3 705 #define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x)) 706 #endif 707 708 /* 709 * ** Byte[x] of bit32 to bit8 710 * */ 711 #ifndef DMA_BIT32_B0_TO_BIT8 712 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 713 #endif 714 715 #ifndef DMA_BIT32_B1_TO_BIT8 716 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 717 #endif 718 719 #ifndef DMA_BIT32_B2_TO_BIT8 720 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 721 #endif 722 723 #ifndef DMA_BIT32_B3_TO_BIT8 724 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 725 #endif 726 727 /*| | 728 | end of DMA access macros for BIG ENDIAN | 729 --------------------------------------------------------------------- 730 */ 731 #else 732 733 #error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN 734 735 #endif /* DMA endian */ 736 /* 737 * End of DMA buffer access macros * 738 * * 739 ********************************************************************** 740 */ 741 742 /************************************************************************************ 743 * * 744 * Constants defined for LL Layer starts * 745 * * 746 ************************************************************************************/ 747 748 /********************************************************* 749 * sTSDK LL revision and Interface revision, FW version 750 *********************************************************/ 751 752 #define FW_THIS_VERSION_SPC12G 0x03060005 753 754 #define FW_THIS_VERSION_SPC6G 0x02092400 755 #define FW_THIS_VERSION_SPC 0x01110000 756 757 758 #define STSDK_LL_INTERFACE_VERSION 0x20A 759 #define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02030401 */ 760 #define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G /**< current sTSDK version */ 761 #define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G /**< FW */ 762 #define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G /**< current V matching FW version */ 763 #define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000 /**< 2.00 FW */ 764 765 #define STSDK_LL_12G_INTERFACE_VERSION 0x302 766 #define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G /**< current sTSDK version */ 767 #define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G /**< FW */ 768 #define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G /**< current V matching FW version */ 769 #define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000 /**< 3.00 FW */ 770 771 #define STSDK_LL_SPC_VERSION 0x01100000 /**< current SPC FW version supported */ 772 #define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC /**< current SPC matching FW version */ 773 #define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502 /**< 1.06d FW */ 774 775 #define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00 776 /************************************************* 777 * constants for API return values 778 *************************************************/ 779 #define AGSA_RC_SUCCESS 0x00 /**< Successful function return value */ 780 #define AGSA_RC_FAILURE 0x01 /**< Failed function return value */ 781 #define AGSA_RC_BUSY 0x02 /**< Busy function return value */ 782 /* current only return from saGetControllerInfo() and saGetControllerStatus() */ 783 #define AGSA_RC_HDA_NO_FW_RUNNING 0x03 /**< HDA mode and no FW running */ 784 #define AGSA_RC_FW_NOT_IN_READY_STATE 0x04 /**< FW not in ready state */ 785 /* current only return from saInitialize() for version checking */ 786 #define AGSA_RC_VERSION_INCOMPATIBLE 0x05 /**< Version mismatch */ 787 #define AGSA_RC_VERSION_UNTESTED 0x06 /**< Version not tested */ 788 #define AGSA_RC_NOT_SUPPORTED 0x07 /**< Operation not supported on the current hardware */ 789 #define AGSA_RC_COMPLETE 0x08 790 791 /************************************************* 792 * constants for type field in agsaMem_t 793 *************************************************/ 794 #define AGSA_CACHED_MEM 0x00 /**< CACHED memory type */ 795 #define AGSA_DMA_MEM 0x01 /**< DMA memory type */ 796 #define AGSA_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */ 797 798 #ifdef SA_ENABLE_TRACE_FUNCTIONS 799 #ifdef FAST_IO_TEST 800 #define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 801 #else 802 #define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 803 #endif 804 #else 805 #ifdef FAST_IO_TEST 806 #define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 807 #else 808 #define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 809 #endif 810 #endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 811 812 813 /********************************** 814 * default constant for phy count 815 **********************************/ 816 #define AGSA_MAX_VALID_PHYS 16 /* was 8 for SPC */ /**< max # of phys supported by the hardware */ 817 818 /************************************ 819 * default constant for Esgl entries 820 ************************************/ 821 #define MAX_ESGL_ENTRIES 10 /**< max # of extended SG list entry */ 822 823 /******************************************* 824 * constant for max inbound/outbound queues 825 *******************************************/ 826 #define AGSA_MAX_INBOUND_Q 64 /**< max # of inbound queue */ 827 #define AGSA_MAX_OUTBOUND_Q 64 /**< max # of outbound queue */ 828 #define AGSA_MAX_BEST_INBOUND_Q 16 /* Max inbound Q number with good IO performance */ 829 830 /**************************** 831 * Phy Control constants 832 ****************************/ 833 #define AGSA_PHY_LINK_RESET 0x01 834 #define AGSA_PHY_HARD_RESET 0x02 835 #define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyControl */ 836 #define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */ 837 #define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */ 838 #define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10 839 #define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12 840 #define AGSA_PHY_COMINIT_OOB 0x20 841 842 #define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */ 843 #define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After capturing the errors, the hardware error counters are cleared and restarted. */ 844 #define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandwidth counters. */ 845 #define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */ 846 #define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY specified in the phyID parameter */ 847 #define AGSA_PHY_SNW3_PAGE 0x06 848 #define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */ 849 #define AGSA_SAS_PHY_MISC_PAGE 0x08 850 #define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and backoff threshold parameters. */ 851 852 /***************** 853 * HW Reset 854 *****************/ 855 #define AGSA_CHIP_RESET 0x00 /**< flag to reset hard reset */ 856 #define AGSA_SOFT_RESET 0x01 /**< flag to reset the controller chip */ 857 858 /*************************************** 859 * Discovery Types 860 ***************************************/ 861 #define AG_SA_DISCOVERY_TYPE_SAS 0x00 /**< flag to discover SAS devices */ 862 #define AG_SA_DISCOVERY_TYPE_SATA 0x01 /**< flag to discover SATA devices */ 863 864 /*************************************** 865 * Discovery Options 866 ***************************************/ 867 #define AG_SA_DISCOVERY_OPTION_FULL_START 0x00 /**< flag to start full discovery */ 868 #define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< flag to start incremental discovery */ 869 #define AG_SA_DISCOVERY_OPTION_ABORT 0x02 /**< flag to abort a discovery */ 870 871 /**************************************************************** 872 * SSP/SMP/SATA Request type 873 ****************************************************************/ 874 /* bit31-28 - request type 875 bit27-16 - reserved 876 bit15-10 - SATA ATAP 877 bit9-8 - direction 878 bit7 - AUTO 879 bit6 - reserved 880 bit5 - EXT 881 bit4 - MSG 882 bit3-0 - Initiator, target or task mode (1 to 8) 883 */ 884 #define AGSA_REQTYPE_MASK 0xF0000000 /**< request type mask */ 885 #define AGSA_REQ_TYPE_UNKNOWN 0x00000000 /**< unknown request type */ 886 #define AGSA_SSP_REQTYPE 0x80000000 887 #define AGSA_SMP_REQTYPE 0x40000000 888 #define AGSA_SATA_REQTYPE 0x20000000 889 890 #define AGSA_DIR_MASK 0x00000300 891 #define AGSA_AUTO_MASK 0x00000080 892 #define AGSA_SATA_ATAP_MASK 0x0000FC00 893 894 #define AGSA_DIR_NONE 0x00000000 895 #define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100 /**< used to be called AGSA_DIR_READ */ 896 #define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200 /**< used to be called AGSA_DIR_WRITE */ 897 898 /* bit definition - AUTO mode */ 899 #define AGSA_AUTO_GOOD_RESPONSE 0x00000080 900 901 /* request type - not bit difination */ 902 #define AGSA_SSP_INIT 0x00000001 903 #define AGSA_SSP_TGT_MODE 0x00000003 904 #define AGSA_SSP_TASK_MGNT 0x00000005 905 #define AGSA_SSP_TGT_RSP 0x00000006 906 #define AGSA_SMP_INIT 0x00000007 907 #define AGSA_SMP_TGT 0x00000008 908 909 /* request type for SSP Initiator and extend */ 910 #define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT) 911 912 /* request type for SSP Initiator and indirect */ 913 #define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT) 914 915 /* bit definition */ 916 #define AGSA_MSG 0x00000010 917 #define AGSA_SSP_EXT_BIT 0x00000020 918 #define AGSA_SSP_INDIRECT_BIT 0x00000040 919 #define AGSA_MSG_BIT AGSA_MSG >> 2 920 921 /* agsaSSPIniEncryptIOStartCmd_t dirMTlr bits*/ 922 #define AGSA_INDIRECT_CDB_BIT 0x00000008 923 #define AGSA_SKIP_MASK_BIT 0x00000010 924 #define AGSA_ENCRYPT_BIT 0x00000020 925 #define AGSA_DIF_BIT 0x00000040 926 #define AGSA_DIF_LA_BIT 0x00000080 927 #define AGSA_DIRECTION_BITS 0x00000300 928 #define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000 929 #define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000 930 931 /* agsaSSPTgtIOStartCmd_t INITagAgrDir bits */ 932 #define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */ 933 #define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */ 934 #define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */ 935 #define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */ 936 #define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */ 937 #define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */ 938 #define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */ 939 #define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */ 940 #define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */ 941 #define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */ 942 #define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */ 943 #define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */ 944 #define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */ 945 946 947 /* agsaSSPIniEncryptIOStartCmd_t DIF_flags bit definitions */ 948 #define AGSA_DIF_UPDATE_BITS 0xFC000000 949 #define AGSA_DIF_VERIFY_BITS 0x03F00000 950 #define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000 951 #define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040 952 #define AGSA_DIF_CRC_SEED_BIT 0x00000020 953 #define AGSA_DIF_CRC_INVERT_BIT 0x00000010 954 #define AGSA_DIF_CRC_VERIFY_BIT 0x00000008 955 #define AGSA_DIF_OP_BITS 0x00000007 956 957 #define AGSA_DIF_OP_INSERT 0x00000000 958 #define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001 959 #define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002 960 #define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003 961 #define AGSA_DIF_OP_RESERVED2 0x00000004 962 #define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005 963 #define AGSA_DIF_OP_RESERVED3 0x00000006 964 #define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007 965 966 967 /* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsLo bit definitions */ 968 #define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000 969 #define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010 970 #define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C 971 #define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002 972 973 /* Cipher mode to be used for this I/O. */ 974 #define AGSA_ENCRYPT_ECB_Mode 0 975 #define AGSA_ENCRYPT_XTS_Mode 0x6 976 977 /* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsHi bit definitions */ 978 #define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0 979 #define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F 980 981 /* defined in the sTSDK spec. */ 982 #define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT) /**< SSP initiator non data request type */ 983 #define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT) /**< SSP initiator read request type */ 984 #define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT) /**< SSP initiator write request type */ 985 #define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ 986 #define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ 987 #define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target read data with automatic good response request type */ 988 #define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ 989 #define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ 990 #define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target write data request type with automatic good response request type*/ 991 #define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT) /**< SSP task management request type */ 992 #define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP) /**< SSP command or task management response request type */ 993 #define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT) /**< SMP initiator request type */ 994 #define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT) /**< SMP target response request type */ 995 #define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG) 996 #define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG) 997 #define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG) 998 #define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT) /**< SSP initiator read request Ext type */ 999 #define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT) /**< SSP initiator write request Ext type */ 1000 1001 #define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator read request indirect type */ 1002 #define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator write request indirect type */ 1003 1004 #define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator read request indirect type */ 1005 #define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator write request indirect type */ 1006 #define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG) 1007 #define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG) 1008 1009 #define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF 1010 1011 #define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400 1012 #define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800 1013 #define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00 1014 #define AGSA_SATA_ATAP_NON_DATA 0x00001000 1015 #define AGSA_SATA_ATAP_PIO 0x00001400 1016 #define AGSA_SATA_ATAP_DMA 0x00001800 1017 #define AGSA_SATA_ATAP_NCQ 0x00001C00 1018 #define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000 1019 #define AGSA_SATA_ATAP_PKT 0x00002400 1020 1021 #define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA) 1022 #define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ 1023 #define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ 1024 #define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ 1025 #define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ 1026 #define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ 1027 #define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ 1028 #define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET) /**< SATA device reset request type */ 1029 #define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT) /**< SATA device reset assert */ 1030 #define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT) /**< SATA device reset deassert */ 1031 #define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT) 1032 #define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT) 1033 #define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT) 1034 1035 1036 #define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG) 1037 #define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ 1038 #define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ 1039 #define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ 1040 #define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ 1041 #define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ 1042 #define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ 1043 #define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1044 #define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1045 #define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1046 /* TestBase */ 1047 #define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG) /**< SATA device reset request type */ 1048 1049 1050 1051 #define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF /**< flag indicates handles interrupts for all channles */ 1052 1053 /**************************************************************************** 1054 ** INBOUND Queue related macros 1055 ****************************************************************************/ 1056 #define AGSA_IBQ_PRIORITY_NORMAL 0x0 1057 #define AGSA_IBQ_PRIORITY_HIGH 0x1 1058 1059 /**************************************************************************** 1060 ** Phy properties related macros 1061 ****************************************************************************/ 1062 /* link rate */ 1063 #define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */ 1064 #define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */ 1065 #define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */ 1066 #define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */ 1067 #define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */ 1068 1069 /* SAS/SATA mode */ 1070 #define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */ 1071 #define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */ 1072 #define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */ 1073 1074 /* control spin-up hold */ 1075 #define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */ 1076 #define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */ 1077 #define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */ 1078 1079 /**************************************************************************** 1080 ** Device Info related macros 1081 ****************************************************************************/ 1082 /* S (SAS/SATA) */ 1083 #define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */ 1084 #define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */ 1085 #define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */ 1086 1087 /* Rate (link-rate) */ 1088 #define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */ 1089 #define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */ 1090 #define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */ 1091 #define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */ 1092 #define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */ 1093 1094 /* devType */ 1095 #define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */ 1096 #define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */ 1097 #define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */ 1098 #define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */ 1099 1100 /***************************************************************************** 1101 ** SAS TM Function definitions see SAS spec p308 Table 105 (Revision 7) 1102 *****************************************************************************/ 1103 #define AGSA_ABORT_TASK 0x01 1104 #define AGSA_ABORT_TASK_SET 0x02 1105 #define AGSA_CLEAR_TASK_SET 0x04 1106 #define AGSA_LOGICAL_UNIT_RESET 0x08 1107 #define AGSA_IT_NEXUS_RESET 0x10 1108 #define AGSA_CLEAR_ACA 0x40 1109 #define AGSA_QUERY_TASK 0x80 1110 #define AGSA_QUERY_TASK_SET 0x81 1111 #define AGSA_QUERY_UNIT_ATTENTION 0x82 1112 1113 /***************************************************************************** 1114 ** SAS TM Function Response Code see SAS spec p312 Table 111 (Revision 7) 1115 *****************************************************************************/ 1116 #define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 1117 #define AGSA_INVALID_FRAME 0x2 1118 #define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4 1119 #define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 1120 #define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 1121 #define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9 1122 /* SAS spec 9.2.2.5.3 p356 Table 128 (Revision 9e) */ 1123 #define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA 1124 1125 #define AGSA_SATA_BSY_OVERRIDE 0x00080000 1126 #define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000 1127 1128 #define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40 1129 #define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36 1130 1131 /* SATA Initiator Request option field defintion */ 1132 #define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001 1133 #define AGSA_SATA_ENABLE_ENCRYPTION 0x000004 1134 #define AGSA_SATA_ENABLE_DIF 0x000008 1135 #define AGSA_SATA_SKIP_QWORD 0xFFFF00 1136 1137 /* SAS Initiator Request flag definitions */ 1138 /* Bits 0,1 use TLR_MASK */ 1139 1140 #define AGSA_SAS_ENABLE_ENCRYPTION 0x0004 1141 #define AGSA_SAS_ENABLE_DIF 0x0008 1142 1143 #ifdef SAFLAG_USE_DIF_ENC_IOMB 1144 #define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010 1145 #endif /* SAFLAG_USE_DIF_ENC_IOMB */ 1146 1147 #define AGSA_SAS_ENABLE_SKIP_MASK 0x0010 1148 #define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0 1149 1150 /**************************************************************************** 1151 ** SMP Phy control Phy Operation field 1152 ****************************************************************************/ 1153 #define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1 1154 #define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2 1155 #define AGSA_PHY_CONTROL_DISABLE 0x3 1156 #define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5 1157 #define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6 1158 #define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7 1159 1160 /**************************************************************************** 1161 ** SAS Diagnostic Operation code 1162 ****************************************************************************/ 1163 #define AGSA_SAS_DIAG_START 0x1 1164 #define AGSA_SAS_DIAG_END 0x0 1165 1166 /**************************************************************************** 1167 ** Port Control constants 1168 ****************************************************************************/ 1169 #define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1 1170 #define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2 1171 #define AGSA_PORT_IO_ABORT 0x3 1172 #define AGSA_PORT_SET_PORT_RESET_TIME 0x4 1173 #define AGSA_PORT_HARD_RESET 0x5 1174 #define AGSA_PORT_CLEAN_UP 0x6 1175 #define AGSA_STOP_PORT_RECOVERY_TIMER 0x7 1176 1177 /* Device State */ 1178 #define SA_DS_OPERATIONAL 0x1 1179 #define SA_DS_PORT_IN_RESET 0x2 1180 #define SA_DS_IN_RECOVERY 0x3 1181 #define SA_DS_IN_ERROR 0x4 1182 #define SA_DS_NON_OPERATIONAL 0x7 1183 1184 /************************************************************************************ 1185 * * 1186 * Constants defined for LL Layer ends * 1187 * * 1188 ************************************************************************************/ 1189 1190 /************************************************************************************ 1191 * * 1192 * Constants defined for OS Layer starts * 1193 * * 1194 ************************************************************************************/ 1195 /***************************************** 1196 * ossaXXX return values 1197 ******************************************/ 1198 /* common for all ossaXXX CB */ 1199 #define OSSA_SUCCESS 0x00 /**< flag indicates successful callback status */ 1200 #define OSSA_FAILURE 0x01 /**< flag indicates failed callback status */ 1201 1202 /* ossaHwCB() */ 1203 #define OSSA_RESET_PENDING 0x03 /**< flag indicates reset pending callback status */ 1204 #define OSSA_CHIP_FAILED 0x04 /**< flag indicates chip failed callback status */ 1205 #define OSSA_FREEZE_FAILED 0x05 /**< flag indicates freeze failed callback status */ 1206 1207 /* ossaLocalPhyControl() */ 1208 #define OSSA_PHY_CONTROL_FAILURE 0x03 /**< flag indicates phy Control operation failure */ 1209 1210 /* ossaDeviceRegisterCB() */ 1211 #define OSSA_FAILURE_OUT_OF_RESOURCE 0x01 /**< flag indicates failed callback status */ 1212 #define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /**< flag indicates failed callback status */ 1213 #define OSSA_FAILURE_INVALID_PHY_ID 0x03 /**< flag indicates failed callback status */ 1214 #define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /**< flag indicates failed callback status */ 1215 #define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /**< flag indicates failed callback status */ 1216 #define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06 /**< flag indicates failed callback status */ 1217 #define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /**< flag indicates failed callback status */ 1218 #define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 1219 #define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021 1220 #define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022 1221 1222 #define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027 /**/ 1223 1224 #define OSSA_ERR_PORT_INVALID 0x1041 1225 #define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042 1226 1227 #define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 1228 1229 #define OSSA_ERR_PHY_ID_INVALID 0x1061 1230 #define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 1231 1232 1233 1234 /* ossaDeregisterDeviceCB() */ 1235 #define OSSA_INVALID_HANDLE 0x02 /**< flag indicates failed callback status */ 1236 #define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The device handle associated with DEVICE_ID does not exist. */ 1237 #define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outstanding I/Os. */ 1238 1239 1240 #define OSSA_RC_ACCEPT 0x00 /**< flag indicates the result of the callback function */ 1241 #define OSSA_RC_REJECT 0x01 /**< flag indicates the result of the callback function */ 1242 1243 /* ossaSetDeviceStateCB() */ 1244 #define OSSA_INVALID_STATE 0x0001 1245 #define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025 1246 #define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026 1247 #define OSSA_ERR_DEVICE_STATE_INVALID 0x0049 1248 1249 /* status of ossaSASDiagExecuteCB() */ 1250 #define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */ 1251 #define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */ 1252 #define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. This is applicable only to the SPCv controller. */ 1253 #define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is applicable only to the SPC controller. */ 1254 #define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic command but PHY is not in diagnostic mode */ 1255 #define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */ 1256 #define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic. This is applicable only to the SPCv controller. */ 1257 1258 1259 /* status of ossaSASDiagStartEndCB() */ 1260 #define OSSA_DIAG_SE_SUCCESS 0x00 1261 #define OSSA_DIAG_SE_INVALID_PHY_ID 0x01 1262 #define OSSA_DIAG_PHY_NOT_DISABLED 0x02 1263 #define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */ 1264 #define OSSA_DIAG_OPCODE_INVALID 0x03 1265 1266 /* status of ossaPortControlCB() */ 1267 #define OSSA_PORT_CONTROL_FAILURE 0x03 1268 1269 #define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004 1270 #define OSSA_MPI_ERR_PORT_INVALID 0x1041 /**/ 1271 #define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043 /**/ 1272 #define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 /**/ 1273 #define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045 /**/ 1274 #define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /**/ 1275 1276 /*regDumpNum of agsaRegDumpInfo_t */ 1277 #define GET_GSM_SM_INFO 0x02 1278 #define GET_IOST_RB_INFO 0x03 1279 1280 /************************************************************************************ 1281 * HW Events 1282 ************************************************************************************/ 1283 #define OSSA_HW_EVENT_RESET_START 0x01 /**< flag indicates reset started event */ 1284 #define OSSA_HW_EVENT_RESET_COMPLETE 0x02 /**< flag indicates chip reset completed event */ 1285 #define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03 /**< flag indicates phy stop event status */ 1286 #define OSSA_HW_EVENT_SAS_PHY_UP 0x04 /**< flag indicates SAS link up event */ 1287 #define OSSA_HW_EVENT_SATA_PHY_UP 0x05 /**< flag indicates SATA link up event */ 1288 #define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06 /**< flag indicates SATA spinup hold event */ 1289 #define OSSA_HW_EVENT_PHY_DOWN 0x07 /**< flag indicates link down event */ 1290 1291 #define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09 /**< flag indicates broadcast change event */ 1292 /* not used spcv 0x0A*/ 1293 #define OSSA_HW_EVENT_PHY_ERROR 0x0A /**< flag indicates link error event */ 1294 #define OSSA_HW_EVENT_BROADCAST_SES 0x0B /**< flag indicates broadcast change (SES) event */ 1295 #define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C 1296 #define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D /**< flag indicates hardware reset received event */ 1297 /* not used spcv 0x0E*/ 1298 #define OSSA_HW_EVENT_MALFUNCTION 0x0E /**< flag indicates unrecoverable Error */ 1299 #define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F /**< flag indicates ID Frame Timeout event */ 1300 #define OSSA_HW_EVENT_BROADCAST_EXP 0x10 /**< flag indicates broadcast (EXPANDER) event */ 1301 /* not used spcv 0x11*/ 1302 #define OSSA_HW_EVENT_PHY_START_STATUS 0x11 /**< flag indicates phy start event status */ 1303 #define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12 /**< flag indicates Link error invalid DWORD */ 1304 #define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13 /**< flag indicates Phy error disparity */ 1305 #define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14 /**< flag indicates Phy error code violation */ 1306 #define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15 /**< flag indicates Link error loss of DWORD synch */ 1307 #define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16 /**< flag indicates Link error phy reset failed */ 1308 #define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 /**< flag indicates Port Recovery timeout */ 1309 #define OSSA_HW_EVENT_PORT_RECOVER 0x18 /**< flag indicates Port Recovery */ 1310 #define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19 /**< flag indicates Port Reset Timer out */ 1311 #define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20 /**< flag indicates Port Reset Complete */ 1312 #define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21 /**< flag indicates Broadcast Asynch Event */ 1313 #define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22 /**< Custom: H/W event for IT Nexus Loss */ 1314 1315 #define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25 1316 1317 #define OSSA_HW_EVENT_ENCRYPTION 0x83 /**< TSDK internal flag indicating that an encryption event occurred */ 1318 #define OSSA_HW_EVENT_MODE 0x84 /**< TSDK internal flag indicating that a controller mode page operation completed */ 1319 #define OSSA_HW_EVENT_SECURITY_MODE 0x85 /**< TSDK internal flag indicating that saEncryptSetMode() completed */ 1320 1321 1322 /* port state */ 1323 #define OSSA_PORT_NOT_ESTABLISHED 0x00 /**< flag indicates port is not established */ 1324 #define OSSA_PORT_VALID 0x01 /**< flag indicates port valid */ 1325 #define OSSA_PORT_LOSTCOMM 0x02 /**< flag indicates port lost communication */ 1326 #define OSSA_PORT_IN_RESET 0x04 /**< flag indicates port in reset state */ 1327 #define OSSA_PORT_3RDPARTY_RESET 0x07 /**< flag indicates port in 3rd party reset state */ 1328 #define OSSA_PORT_INVALID 0x08 /**< flag indicates port invalid */ 1329 1330 /* status for agsaHWEventMode_t */ 1331 #define OSSA_CTL_SUCCESS 0x0000 1332 #define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001 1333 #define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002 1334 #define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 1335 #define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004 1336 #define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005 1337 // #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B 1338 #define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX 1339 1340 1341 1342 /************************************************************************************ 1343 * General Events value 1344 ************************************************************************************/ 1345 #define OSSA_INBOUND_V_BIT_NOT_SET 0x01 1346 #define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02 1347 #define OSSA_INBOUND_IOMB_INVALID_OBID 0x03 1348 1349 /************************************************************************************ 1350 * FW Flash Update status values 1351 ************************************************************************************/ 1352 #define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 /**< flag indicates fw flash update completed */ 1353 #define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01 /**< flag indicates fw flash update in progress */ 1354 #define OSSA_FLASH_UPDATE_HDR_ERR 0x02 /**< flag indicates fw flash header error */ 1355 #define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset error */ 1356 #define OSSA_FLASH_UPDATE_CRC_ERR 0x04 /**< flag indicates fw flash CRC error */ 1357 #define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05 /**< flag indicates fw flash length error */ 1358 #define OSSA_FLASH_UPDATE_HW_ERR 0x06 /**< flag indicates fw flash HW error */ 1359 #define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E /**< flag indicates fw flash Firmware image HMAC authentication failure.*/ 1360 1361 #define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 /**< flag indicates fw flash down load not supported */ 1362 #define OSSA_FLASH_UPDATE_DISABLED 0x11 /**< flag indicates fw flash Update disabled */ 1363 #define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12 /**< flag indicates fw flash Update disabled */ 1364 1365 /************************************************************************************ 1366 * Discovery status values 1367 ************************************************************************************/ 1368 #define OSSA_DISCOVER_STARTED 0x00 /**< flag indicates discover started */ 1369 #define OSSA_DISCOVER_FOUND_DEVICE 0x01 /**< flag indicates discovery found a new device */ 1370 #define OSSA_DISCOVER_REMOVED_DEVICE 0x02 /**< flag indicates discovery found a device removed */ 1371 #define OSSA_DISCOVER_COMPLETE 0x03 /**< flag indicates discover completed */ 1372 #define OSSA_DISCOVER_ABORT 0x04 /**< flag indicates discover error12 */ 1373 #define OSSA_DISCOVER_ABORT_ERROR_1 0x05 /**< flag indicates discover error1 */ 1374 #define OSSA_DISCOVER_ABORT_ERROR_2 0x06 /**< flag indicates discover error2 */ 1375 #define OSSA_DISCOVER_ABORT_ERROR_3 0x07 /**< flag indicates discover error3 */ 1376 #define OSSA_DISCOVER_ABORT_ERROR_4 0x08 /**< flag indicates discover error4 */ 1377 #define OSSA_DISCOVER_ABORT_ERROR_5 0x09 /**< flag indicates discover error5 */ 1378 #define OSSA_DISCOVER_ABORT_ERROR_6 0x0A /**< flag indicates discover error6 */ 1379 #define OSSA_DISCOVER_ABORT_ERROR_7 0x0B /**< flag indicates discover error7 */ 1380 #define OSSA_DISCOVER_ABORT_ERROR_8 0x0C /**< flag indicates discover error8 */ 1381 #define OSSA_DISCOVER_ABORT_ERROR_9 0x0D /**< flag indicates discover error9 */ 1382 1383 /*********************************************************************************** 1384 * Log Debug Levels 1385 ***********************************************************************************/ 1386 #define OSSA_DEBUG_LEVEL_0 0x00 /**< debug level 0 */ 1387 #define OSSA_DEBUG_LEVEL_1 0x01 /**< debug level 1 */ 1388 #define OSSA_DEBUG_LEVEL_2 0x02 /**< debug level 2 */ 1389 #define OSSA_DEBUG_LEVEL_3 0x03 /**< debug level 3 */ 1390 #define OSSA_DEBUG_LEVEL_4 0x04 /**< debug level 4 */ 1391 1392 #define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed by OS layer */ 1393 1394 #define OSSA_FRAME_TYPE_SSP_CMD 0x06 /**< flag indicates received frame is SSP command */ 1395 #define OSSA_FRAME_TYPE_SSP_TASK 0x16 /**< flag indicates received frame is SSP task management */ 1396 1397 /* Event Source Type of saRegisterEventCallback() */ 1398 #define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00 1399 #define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01 1400 1401 /* Status of Get Device Info CB */ 1402 #define OSSA_DEV_INFO_INVALID_HANDLE 0x01 1403 #define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02 1404 #define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03 1405 #define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04 1406 1407 /* Diagnostic Command Type */ 1408 #define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00 1409 #define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01 1410 #define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02 1411 #define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03 1412 #define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04 1413 #define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05 1414 1415 /* Command Description for CMD_TYPE DIAG_OPRN_PERFORM, DIAG_OPRN_STOP, THRESHOLD_SPECIFY */ 1416 #define AGSA_CMD_DESC_PRBS 0x00 1417 #define AGSA_CMD_DESC_CJTPAT 0x01 1418 #define AGSA_CMD_DESC_USR_PATTERNS 0x02 1419 #define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08 1420 #define AGSA_CMD_DESC_PRBS_INVERT 0x09 1421 #define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A 1422 #define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B 1423 #define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C 1424 #define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E 1425 #define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10 1426 #define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11 1427 #define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12 1428 1429 /* Command Description for CMD_TYPE DIAG_REPORT_GET and ERR_CNT_RESET */ 1430 #define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00 1431 #define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01 1432 #define AGSA_CMD_DESC_DISP_ERR_CNT 0x02 1433 #define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05 1434 #define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06 1435 #define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09 1436 #define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A 1437 #define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B 1438 #define AGSA_CMD_DESC_PHY_RST_CNT 0x0C 1439 #define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E 1440 1441 #define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19 1442 #define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A 1443 #define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B 1444 #define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C 1445 #define AGSA_CMD_DESC_ALL 0x1F 1446 1447 /* NVMDevice type */ 1448 #define AGSA_NVMD_TWI_DEVICES 0x00 1449 #define AGSA_NVMD_CONFIG_SEEPROM 0x01 1450 #define AGSA_NVMD_VPD_FLASH 0x04 1451 #define AGSA_NVMD_AAP1_REG_FLASH 0x05 1452 #define AGSA_NVMD_IOP_REG_FLASH 0x06 1453 #define AGSA_NVMD_EXPANSION_ROM 0x07 1454 #define AGSA_NVMD_REG_FLASH 0x05 1455 1456 1457 /* GET/SET NVMD Data Response errors */ 1458 #define OSSA_NVMD_SUCCESS 0x0000 1459 #define OSSA_NVMD_MODE_ERROR 0x0001 1460 #define OSSA_NVMD_LENGTH_ERROR 0x0002 1461 #define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005 1462 #define OSSA_NVMD_TWI_NACK_ERROR 0x2001 1463 #define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002 1464 #define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021 1465 #define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081 1466 #define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082 1467 #define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF 1468 #define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001 1469 #define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002 1470 #define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003 1471 #define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004 1472 #define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005 1473 #define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006 1474 #define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007 1475 #define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008 1476 #define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009 1477 #define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A 1478 #define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B 1479 #define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C 1480 #define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D 1481 #define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E 1482 1483 /************************************************************ 1484 * ossaHwCB Encryption encryptOperation of agsaHWEventEncrypt_t 1485 ************************************************************/ 1486 #define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000 1487 #define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001 1488 #define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002 1489 #define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003 1490 #define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004 1491 #define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005 1492 #define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006 1493 #define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007 1494 #define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008 1495 1496 1497 /************************************************************ 1498 * ossaHwCB Encryption status of agsaHWEventEncrypt_t 1499 ************************************************************/ 1500 /* KEK and DEK managment status from PM */ 1501 #define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 1502 #define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/ 1503 #define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000 1504 #define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001 1505 #define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002 1506 #define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021 1507 #define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022 1508 #define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023 1509 1510 /*encrypt operator management response status */ 1511 #define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060 1512 #define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 1513 #define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 1514 #define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 1515 #define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 1516 1517 /*encrypt saSetOperator() response status */ 1518 #define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005 1519 #define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B 1520 1521 /* agsaEncryptSMX | agsaEncryptCipherMode == cipherMode for saEncryptSetMode()*/ 1522 /* Make sure all definitions are unique bits */ 1523 #define agsaEncryptSMF 0x00000000 1524 #define agsaEncryptSMA 0x00000100 1525 #define agsaEncryptSMB 0x00000200 1526 #define agsaEncryptReturnSMF (1 << 12) 1527 #define agsaEncryptAuthorize (1 << 13) 1528 1529 /* 1530 Bits 16-23: Allowable Cipher Mode(ACM) 1531 Bit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled. 1532 Bit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled. 1533 */ 1534 #define agsaEncryptAcmMask 0x00ff0000 1535 #define agsaEncryptEnableAES_ECB (1 << 16) 1536 #define agsaEncryptEnableAES_XTS (1 << 22) 1537 1538 1539 1540 #define agsaEncryptCipherModeECB 0x00000001 1541 #define agsaEncryptCipherModeXTS 0x00000002 1542 1543 1544 1545 #define agsaEncryptStatusNoNVRAM 0x00000001 1546 #define agsaEncryptStatusNVRAMErr 0x00000002 1547 1548 /* 1549 1550 Bin Hex Sector Total 1551 00000 :0x0 512B 512 1552 11000 :0x1 520B 520 1553 00010 :0x2 4K 4096 1554 00011 :0x3 4K+64B 4160 1555 00100 :0x4 4K+128B 4224 1556 1557 11000 :0x18 512+8B 520 1558 11001 :0x19 520+8B 528 1559 11010 :0x1A 4K+8B 4104 1560 11011 :0x1B 4K+64B+8B 4168 1561 11100 :0x1C 4K+128B+8B 4232 1562 1563 */ 1564 1565 #define agsaEncryptSectorSize512 0 1566 /* define agsaEncryptSectorSize520 1 Not supported */ 1567 #define agsaEncryptSectorSize4096 2 1568 #define agsaEncryptSectorSize4160 3 1569 #define agsaEncryptSectorSize4224 4 1570 1571 #define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18) 1572 #define agsaEncryptDIFSectorSize528 ( 0x19) 1573 #define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18) 1574 #define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18) 1575 #define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18) 1576 1577 1578 #define AGSA_ENCRYPT_STORE_NVRAM 1 1579 1580 /************************************************************ 1581 * ossaHwCB Mode page event definitions 1582 ************************************************************/ 1583 #define agsaModePageGet 1 1584 #define agsaModePageSet 2 1585 1586 /************************************************************ 1587 * saSgpio() SGPIO Function and Register type 1588 ************************************************************/ 1589 #define AGSA_READ_SGPIO_REGISTER 0x02 1590 #define AGSA_WRITE_SGPIO_REGISTER 0x82 1591 1592 #define AGSA_SGPIO_CONFIG_REG 0x0 1593 #define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1 1594 #define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2 1595 #define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3 1596 #define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4 1597 1598 /************************************************************ 1599 * ossaSGpioCB() Function result 1600 ************************************************************/ 1601 #define OSSA_SGPIO_COMMAND_SUCCESS 0x00 1602 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01 1603 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02 1604 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03 1605 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04 1606 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05 1607 #define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06 1608 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19 1609 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81 1610 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A 1611 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82 1612 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83 1613 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D 1614 #define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D 1615 1616 #define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D 1617 #define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C 1618 1619 /************************************************************ 1620 * ossaGetDFEDataCB() status 1621 ************************************************************/ 1622 #define OSSA_DFE_MPI_IO_SUCCESS 0x0000 1623 #define OSSA_DFE_DATA_OVERFLOW 0x0002 1624 #define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004 1625 #define OSSA_DFE_CHANNEL_DOWN 0x100E 1626 #define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F 1627 #define OSSA_DFE_CHANNEL_INVALID 0x1010 1628 #define OSSA_DFE_DMA_FAILURE 0x1011 1629 1630 /************************************************************************************ 1631 * * 1632 * Constants defined for OS Layer ends * 1633 * * 1634 ************************************************************************************/ 1635 1636 /************************************************************************************ 1637 * * 1638 * Data Structures Defined for LL API start * 1639 * * 1640 ************************************************************************************/ 1641 /** \brief data structure stores OS specific and LL specific context 1642 * 1643 * The agsaContext_t data structure contains two generic pointers, 1644 * also known as handles, which are used to store OS Layer-specific and 1645 * LL Layer-specific contexts. Only the handle specific to a layer can 1646 * be modified by the layer. The other layer's handle must be returned 1647 * unmodified when communicating between the layers. 1648 1649 * A layer's handle is typically typecast to an instance of a layer-specific 1650 * data structure. The layer can use its handle to point to any data type 1651 * that is to be associated with a function call. A handle provides a way 1652 * to uniquely identify responses when multiple calls to the same function 1653 * are necessary. 1654 * 1655 */ 1656 typedef struct agsaContext_s 1657 { 1658 void *osData; /**< Pointer-sized value used internally by the OS Layer */ 1659 void *sdkData; /**< Pointer-sized value used internally by the LL Layer */ 1660 } agsaContext_t; 1661 1662 /** \brief hold points to global data structures used by the LL and OS Layers 1663 * 1664 * The agsaRoot_t data structure is used to hold pointer-sized values for 1665 * internal use by the LL and OS Layers. It is intended that the 1666 * sdkData element of the agsaRoot_t data structure be used to 1667 * identify an instance of the hardware context. The sdkData 1668 * element is set by the LL Layer in the saHwInitialize() 1669 * function and returned to the OS Layer in the agsaRoot_t data 1670 * structure 1671 */ 1672 typedef agsaContext_t agsaRoot_t; 1673 1674 /** \brief holds the pointers to the device data structure used by the LL and OS Layers 1675 * 1676 * The agsaDevHandle_t data structure is the device instance handle. 1677 * It holds pointer-sized values used internally by each of the LL and 1678 * OS Layers. It is intended that the agsaDevHandle_t data 1679 * structure be used to identify a specific device instance. A 1680 * device instance is uniquely identified by its device handle. 1681 */ 1682 typedef agsaContext_t agsaDevHandle_t; 1683 1684 /** \brief holds the pointers to the port data structure used by the LL and 1685 * OS Layers 1686 * 1687 * The agsaPortContext_t data structure is used to describe an instance of 1688 * SAS port or SATA port. It holds pointer-sized values used 1689 * internally by each of the LL and OS Layers. 1690 * 1691 * When connected to other SAS end-devices or expanders, each instance of 1692 * agsaPortContext_t represents a SAS local narrow-port or 1693 * wide-port. 1694 * 1695 * When connected to SATA device, each instance of agsaPortContext_t 1696 * represents a local SATA port. 1697 * 1698 */ 1699 typedef agsaContext_t agsaPortContext_t; 1700 1701 /** \brief data structure pointer to IO request structure 1702 * 1703 * It is intended that the agsaIORequest_t structure be used to 1704 * uniquely identify each I/O Request for either target or 1705 * initiator. The OS Layer is responsible for allocating and 1706 * managing agsaIORequest_t structures. The LL Layer uses each 1707 * structure only between calls to: saSSPStart() and 1708 * ossaSSPCompleted(), saSATAStart() and ossaSATACompleted(), 1709 * saSMPStart() and ossaSMPCompleted() 1710 * 1711 */ 1712 typedef agsaContext_t agsaIORequest_t; 1713 1714 /** \brief handle to access frame 1715 * 1716 * This data structure is the handle to access frame 1717 */ 1718 typedef void *agsaFrameHandle_t; 1719 1720 /** \brief describe a SAS ReCofiguration structure in the SAS/SATA hardware 1721 * 1722 * Describe a SAS ReConfiguration in the SAS/SATA hardware 1723 * 1724 */ 1725 typedef struct agsaSASReconfig_s { 1726 bit32 flags; /* flag to indicate a change to the default parameter 1727 bit31-30:reserved 1728 bit29: a change to the default SAS/SATA ports is requested 1729 bit28: the OPEN REJECT (RETRY) in command phase is requested 1730 bit27: the OPEN REJECT (RETRY) in data phase is requested 1731 bit26: REJECT will be mapped into OPEN REJECT 1732 bit25: delay for SATA Head-of-Line blocking detection timeout 1733 bit24-00:reserved */ 1734 bit16 reserved0; /* reserved */ 1735 bit8 reserved1; /* reserved */ 1736 bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */ 1737 bit16 openRejectRetriesCmd; /* This field is valid if bit 28 of the flags field is set to 1 */ 1738 bit16 openRejectRetriesData; /* This field is valid if bit 27 of the flags field is set to 1.*/ 1739 bit16 reserved2; /* reserved */ 1740 bit16 sataHolTmo; /* This field is valid if bit 25 of the flags field is set to 1 */ 1741 } agsaSASReconfig_t; 1742 1743 /** \brief describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware 1744 * 1745 * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware 1746 * 1747 */ 1748 typedef struct agsaPhyAnalogSetupRegisters_s 1749 { 1750 bit32 spaRegister0; 1751 bit32 spaRegister1; 1752 bit32 spaRegister2; 1753 bit32 spaRegister3; 1754 bit32 spaRegister4; 1755 bit32 spaRegister5; 1756 bit32 spaRegister6; 1757 bit32 spaRegister7; 1758 bit32 spaRegister8; 1759 bit32 spaRegister9; 1760 } agsaPhyAnalogSetupRegisters_t; 1761 1762 #define MAX_INDEX 10 1763 1764 /** \brief 1765 * 1766 */ 1767 typedef struct agsaPhyAnalogSetupTable_s 1768 { 1769 agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX]; 1770 } agsaPhyAnalogSetupTable_t; 1771 1772 /** \brief describe a Phy Analog Setting 1773 * 1774 * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware 1775 * 1776 */ 1777 typedef struct agsaPhyAnalogSettingsPage_s 1778 { 1779 bit32 Dword0; 1780 bit32 Dword1; 1781 bit32 Dword2; 1782 bit32 Dword3; 1783 bit32 Dword4; 1784 bit32 Dword5; 1785 bit32 Dword6; 1786 bit32 Dword7; 1787 bit32 Dword8; 1788 bit32 Dword9; 1789 } agsaPhyAnalogSettingsPage_t; 1790 1791 1792 /** \brief describe a Open reject retry backoff threshold page 1793 * 1794 * Describe a Open reject retry backoff threshold registers in the SAS/SATA hardware 1795 * 1796 */ 1797 typedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s 1798 { 1799 bit32 Dword0; 1800 bit32 Dword1; 1801 bit32 Dword2; 1802 bit32 Dword3; 1803 } agsaSASPhyOpenRejectRetryBackOffThresholdPage_t; 1804 1805 /** \brief describe a Phy Rate Control 1806 * 4.56 agsaPhyRateControlPage_t 1807 * Description 1808 * This profile page is used to read or set several rate control 1809 * parameters. The page code for this profile page is 0x07. This page can 1810 * be READ by issuing saGetPhyProfile(). It can be read anytime and there 1811 * is no need to quiesce the I/O to the controller. 1812 * Related parameters can be modified by issuing saSetPhyProfile() before 1813 * calling saPhyStart() to the PHY. 1814 * Note: This page is applicable only to the SPCv controller. 1815 * Usage 1816 * Initiator and target. 1817 */ 1818 typedef struct agsaPhyRateControlPage_s 1819 { 1820 bit32 Dword0; 1821 bit32 Dword1; 1822 bit32 Dword2; 1823 } agsaPhyRateControlPage_t; 1824 1825 /** 1826 * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every 1827 * ALIGN_RATE+1 DWord. The default value results in the standard compliant 1828 * value of 2/256. This rate applies to out of connection, SMP and SSP 1829 * connections. The default value is 0x0ff. Other bits are reserved. 1830 * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in 1831 * every ALIGN_RATE+1 DWords. Default value results in standard compliant 1832 * value of 2/256. This rate applies to out of STP connections. The default 1833 * value is 0x0ff. Other bits are reserved. 1834 * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords 1835 * between each SSP frame. 0 means no idle cycles. The default value is 1836 * 0x0. Other bits are reserved. 1837 **/ 1838 1839 /** \brief describe a Register Dump information for a Controller in the SAS/SATA hardware 1840 * 1841 * Describe a register dump information for a controller in the SAS/SATA hardware 1842 * 1843 */ 1844 typedef struct agsaRegDumpInfo_s 1845 { 1846 bit8 regDumpSrc; 1847 bit8 regDumpNum; 1848 bit8 reserved[2]; 1849 bit32 regDumpOffset; 1850 bit32 directLen; 1851 void *directData; 1852 bit32 indirectAddrUpper32; 1853 bit32 indirectAddrLower32; 1854 bit32 indirectLen; 1855 } agsaRegDumpInfo_t; 1856 1857 /* 1858 7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000] 1859 8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000] 1860 9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1861 10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1862 11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1863 12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1864 13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000] 1865 14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1866 15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1867 16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000] 1868 17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1869 18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1870 19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1871 20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1872 21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1873 22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1874 23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000] 1875 24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000] 1876 25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000] 1877 26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000] 1878 */ 1879 1880 #define TYPE_GSM_SPACE 1 1881 #define TYPE_QUEUE 2 1882 #define TYPE_FATAL 3 1883 #define TYPE_NON_FATAL 4 1884 #define TYPE_INBOUND_QUEUE 5 1885 #define TYPE_OUTBOUND_QUEUE 6 1886 1887 1888 #define BAR_SHIFT_GSM_OFFSET 0x400000 1889 1890 #define ONE_MEGABYTE 0x100000 1891 #define SIXTYFOURKBYTE (1024 * 64) 1892 1893 1894 1895 #define TYPE_INBOUND 1 1896 #define TYPE_OUTBOUND 2 1897 1898 typedef struct 1899 { 1900 bit32 DataType; 1901 union 1902 { 1903 struct 1904 { 1905 bit32 directLen; 1906 bit32 directOffset; 1907 bit32 readLen; 1908 void *directData; 1909 }gsmBuf; 1910 1911 struct 1912 { 1913 bit16 queueType; 1914 bit16 queueIndex; 1915 bit32 directLen; 1916 void *directData; 1917 }queueBuf; 1918 1919 struct 1920 { 1921 bit32 directLen; 1922 bit32 directOffset; 1923 bit32 readLen; 1924 void *directData; 1925 }dataBuf; 1926 } BufferType; 1927 } agsaForensicData_t; 1928 1929 /** \brief describe a NVMData for a Controller in the SAS/SATA hardware 1930 * 1931 * Describe a NVMData for a controller in the SAS/SATA hardware 1932 * 1933 */ 1934 typedef struct agsaNVMDData_s 1935 { 1936 bit32 indirectPayload :1; 1937 bit32 reserved :7; 1938 bit32 TWIDeviceAddress :8; 1939 bit32 TWIBusNumber :4; 1940 bit32 TWIDevicePageSize :4; 1941 bit32 TWIDeviceAddressSize :4; 1942 bit32 NVMDevice :4; 1943 bit32 directLen :8; 1944 bit32 dataOffsetAddress :24; 1945 void *directData; 1946 bit32 indirectAddrUpper32; 1947 bit32 indirectAddrLower32; 1948 bit32 indirectLen; 1949 bit32 signature; 1950 } agsaNVMDData_t; 1951 1952 1953 /* status of ossaPCIeDiagExecuteCB() is shared with ossaSASDiagExecuteCB() */ 1954 #define OSSA_PCIE_DIAG_SUCCESS 0x0000 1955 #define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001 1956 #define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002 1957 #define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006 1958 #define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007 1959 #define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008 1960 #define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009 1961 #define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A 1962 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000 1963 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 1964 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 1965 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 1966 #define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042 1967 #define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 1968 #define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005 1969 1970 1971 typedef struct agsaPCIeDiagExecute_s 1972 { 1973 bit32 command; 1974 bit32 flags; 1975 bit16 initialIOSeed; 1976 bit16 reserved; 1977 bit32 rdAddrLower; 1978 bit32 rdAddrUpper; 1979 bit32 wrAddrLower; 1980 bit32 wrAddrUpper; 1981 bit32 len; 1982 bit32 pattern; 1983 bit8 udtArray[6]; 1984 bit8 udrtArray[6]; 1985 } agsaPCIeDiagExecute_t; 1986 1987 1988 /** \brief agsaPCIeDiagResponse_t 1989 * 1990 * status of ossaPCIeDiagExecuteCB() 1991 * The agsaPCIeDiagResponse_t structure is a parameter passed to 1992 * ossaPCIeDiagExecuteCB() 1993 * to contain a PCIe Diagnostic command response. 1994 */ 1995 1996 typedef struct agsaPCIeDiagResponse_s { 1997 bit32 ERR_BLKH; 1998 bit32 ERR_BLKL; 1999 bit32 DWord8; 2000 bit32 DWord9; 2001 bit32 DWord10; 2002 bit32 DWord11; 2003 bit32 DIF_ERR; 2004 } agsaPCIeDiagResponse_t; 2005 2006 2007 /** \brief describe a fatal error information for a Controller in the SAS/SATA hardware 2008 * 2009 * Describe a fatal error information for a controller in the SAS/SATA hardware 2010 * 2011 */ 2012 typedef struct agsaFatalErrorInfo_s 2013 { 2014 bit32 errorInfo0; 2015 bit32 errorInfo1; 2016 bit32 errorInfo2; 2017 bit32 errorInfo3; 2018 bit32 regDumpBusBaseNum0; 2019 bit32 regDumpOffset0; 2020 bit32 regDumpLen0; 2021 bit32 regDumpBusBaseNum1; 2022 bit32 regDumpOffset1; 2023 bit32 regDumpLen1; 2024 } agsaFatalErrorInfo_t; 2025 2026 /** \brief describe a information for a Event in the SAS/SATA hardware 2027 * 2028 * Describe a general information for a Event in the SAS/SATA hardware 2029 * 2030 */ 2031 typedef struct agsaEventSource_s 2032 { 2033 agsaPortContext_t *agPortContext; 2034 bit32 event; 2035 bit32 param; 2036 } agsaEventSource_t; 2037 2038 /** \brief describe a information for a Controller in the SAS/SATA hardware 2039 * 2040 * Describe a general information for a controller in the SAS/SATA hardware 2041 * 2042 */ 2043 typedef struct agsaControllerInfo_s 2044 { 2045 bit32 signature; /* coherent controller information */ 2046 bit32 fwInterfaceRev; /* host and controller interface version */ 2047 bit32 hwRevision; /* controller HW Revision number */ 2048 bit32 fwRevision; /* controller FW Revision number */ 2049 bit32 ilaRevision; /* controller ILA Revision number */ 2050 bit32 maxPendingIO; /* maximum number of outstanding I/Os supported */ 2051 bit32 maxDevices; /* Maximum Device Supported by controller */ 2052 bit32 maxSgElements; /* maximum number of SG elements supported */ 2053 bit32 queueSupport; /* maximum number of IQ and OQ supported 2054 bit31-19 reserved 2055 bit18 interrupt coalescing 2056 bit17 reserved 2057 bit16 high priority IQ supported 2058 bit15-08 maximum number of OQ 2059 bit07-00 maximum number of IQ */ 2060 bit8 phyCount; /* number of phy available in the controller */ 2061 bit8 controllerSetting;/* Controller setting 2062 bit07-04 reserved 2063 bit03-00 HDA setting */ 2064 bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */ 2065 bit8 PCIWidth; /* PCI number of lanes */ 2066 bit32 sasSpecsSupport; /* the supported SAS spec. */ 2067 bit32 sdkInterfaceRev; /* sdk interface reversion */ 2068 bit32 sdkRevision; /* sdk reversion */ 2069 } agsaControllerInfo_t; 2070 2071 /** \brief describe a status for a Controller in the SAS/SATA hardware 2072 * 2073 * Describe a general status for a controller in the SAS/SATA hardware 2074 * 2075 */ 2076 typedef struct agsaControllerStatus_s 2077 { 2078 agsaFatalErrorInfo_t fatalErrorInfo; /* fatal error information */ 2079 bit32 interfaceState; /* host and controller interface state 2080 bit02-00 state of host and controller 2081 bit16-03 reserved 2082 bit31-16 detail of error based on error state */ 2083 bit32 iqFreezeState0; /* freeze state of 1st set of IQ */ 2084 bit32 iqFreezeState1; /* freeze state of 2nd set of IQ */ 2085 bit32 tickCount0; /* tick count in second for internal CPU-0 */ 2086 bit32 tickCount1; /* tick count in second for internal CPU-1 */ 2087 bit32 tickCount2; /* tick count in second for internal CPU-2 */ 2088 bit32 phyStatus[8]; /* status of phy 0 to phy 15 */ 2089 bit32 recoverableErrorInfo[8]; /* controller specific recoverable error information */ 2090 bit32 bootStatus; 2091 bit16 bootComponentState[8]; 2092 2093 } agsaControllerStatus_t; 2094 2095 /** \brief describe a GPIO Event Setup Infomation in the SAS/SATA hardware 2096 * 2097 * Describe a configuration for a GPIO Event Setup Infomation in the SAS/SATA hardware 2098 * 2099 */ 2100 typedef struct agsaGpioEventSetupInfo_s 2101 { 2102 bit32 gpioPinMask; 2103 bit32 gpioEventLevel; 2104 bit32 gpioEventRisingEdge; 2105 bit32 gpioEventFallingEdge; 2106 } agsaGpioEventSetupInfo_t; 2107 2108 /** \brief describe a GPIO Pin Setup Infomation in the SAS/SATA hardware 2109 * 2110 * Describe a configuration for a GPIO Pin Setup Infomation in the SAS/SATA hardware 2111 * 2112 */ 2113 typedef struct agsaGpioPinSetupInfo_t 2114 { 2115 bit32 gpioPinMask; 2116 bit32 gpioInputEnabled; 2117 bit32 gpioTypePart1; 2118 bit32 gpioTypePart2; 2119 } agsaGpioPinSetupInfo_t; 2120 2121 /** \brief describe a serial GPIO operation in the SAS/SATA hardware 2122 * 2123 * Describe a configuration for a GPIO write Setup Infomation in the SAS/SATA hardware 2124 * 2125 */ 2126 typedef struct agsaGpioWriteSetupInfo_s 2127 { 2128 bit32 gpioWritemask; 2129 bit32 gpioWriteVal; 2130 }agsaGpioWriteSetupInfo_t; 2131 2132 /** \brief describe a GPIO Read Infomation in the SAS/SATA hardware 2133 * 2134 * Describe a configuration for a GPIO read Infomation in the SAS/SATA hardware 2135 * 2136 */ 2137 typedef struct agsaGpioReadInfo_s 2138 { 2139 bit32 gpioReadValue; 2140 bit32 gpioInputEnabled; /* GPIOIE */ 2141 bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */ 2142 bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */ 2143 bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */ 2144 bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */ 2145 bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */ 2146 bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */ 2147 }agsaGpioReadInfo_t; 2148 2149 /** \brief describe a serial GPIO request and response in the SAS/SATA hardware 2150 * 2151 * Describe the fields required for serial GPIO request and response in the SAS/SATA hardware 2152 * 2153 */ 2154 typedef struct agsaSGpioReqResponse_s 2155 { 2156 bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/ 2157 bit8 function; /* 0x02 for read, 0x82 for write */ 2158 bit8 registerType; /* used only in request */ 2159 bit8 registerIndex; /* used only in request */ 2160 bit8 registerCount; /* used only in request */ 2161 bit8 functionResult; /* used only in response */ 2162 bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; /* write data for request; read data for response */ 2163 } agsaSGpioReqResponse_t; 2164 2165 2166 /** \brief describe a serial GPIO operation response in the SAS/SATA hardware 2167 * 2168 * Describe the fields required for serial GPIO operations response in the SAS/SATA hardware 2169 * 2170 */ 2171 typedef struct agsaSGpioCfg0 2172 { 2173 bit8 reserved1; 2174 bit8 version:4; 2175 bit8 reserved2:4; 2176 bit8 gpRegisterCount:4; 2177 bit8 cfgRegisterCount:3; 2178 bit8 gpioEnable:1; 2179 bit8 supportedDriveCount; 2180 } agsaSGpioCfg0_t; 2181 2182 /** \brief SGPIO configuration register 1 2183 * 2184 * These fields constitute SGPIO configuration register 1, as defined by SFF-8485 spec 2185 * 2186 */ 2187 typedef struct agsaSGpioCfg1{ 2188 bit8 reserved; 2189 bit8 blinkGenA:4; 2190 bit8 blinkGenB:4; 2191 bit8 maxActOn:4; 2192 bit8 forceActOff:4; 2193 bit8 stretchActOn:4; 2194 bit8 stretchActOff:4; 2195 } agsaSGpioCfg1_t; 2196 2197 /** \brief describe a configuration for a PHY in the SAS/SATA hardware 2198 * 2199 * Describe a configuration for a PHY in the SAS/SATA hardware 2200 * 2201 */ 2202 typedef struct agsaPhyConfig_s 2203 { 2204 bit32 phyProperties; 2205 /**< b31-b8 reserved */ 2206 /**< b16-b19 SSC Disable */ 2207 /**< b15-b8 phy analog setup index */ 2208 /**< b7 phy analog setup enable */ 2209 /**< b6 Control spin up hold */ 2210 /**< b5-b4 SAS/SATA mode, bit4 - SAS, bit5 - SATA, 11b - Auto mode */ 2211 /**< b3-b0 Max. Link Rate, bit0 - 1.5Gb/s, bit1 - 3.0Gb/s, 2212 bit2 - 6.0Gb/s, bit3 - reserved */ 2213 } agsaPhyConfig_t; 2214 2215 2216 /** \brief Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter 2217 * 2218 * Description 2219 * This profile page is used to read or set the SNW-3 PHY capabilities of a 2220 * SAS PHY. This page can be read by calling saGetPhyProfile(). It can be 2221 * read anytime and there is no need to quiesce he I/O to the controller. 2222 * The format of the 32-bit SNW3 is the same as defined in the SAS 2 2223 * specification. 2224 * Local SNW3 can be modified by calling saSetPhyProfile() before 2225 * saPhyStart() to the PHY. REQUESTED LOGICAL LINK RATE is reserved. 2226 * The SPCv will calculate the PARITY field. 2227 2228 * Note: This page is applicable only to the SPCv controller. 2229 * Usage 2230 * Initiator and target. 2231 */ 2232 2233 typedef struct agsaPhySNW3Page_s 2234 { 2235 bit32 LSNW3; 2236 bit32 RSNW3; 2237 } agsaPhySNW3Page_t; 2238 2239 /** \brief structure describe error counters of a PHY in the SAS/SATA 2240 * 2241 * Structure is used as a parameter passed in saLocalPhyControlCB() 2242 * to describe the error counter 2243 * 2244 */ 2245 typedef struct agsaPhyErrCounters_s 2246 { 2247 bit32 invalidDword; /* Number of invalid dwords that have been 2248 received outside of phy reset sequences.*/ 2249 bit32 runningDisparityError; /* Number of dwords containing running disparity 2250 errors that have been received outside of phy 2251 reset sequences.*/ 2252 bit32 lossOfDwordSynch; /* Number of times the phy has restarted the link 2253 reset sequence because it lost dword synchronization.*/ 2254 bit32 phyResetProblem; /* Number of times the phy did not obtain dword 2255 synchronization during the final SAS speed 2256 negotiation window.*/ 2257 bit32 elasticityBufferOverflow; /* Number of times the phys receive elasticity 2258 buffer has overflowed.*/ 2259 bit32 receivedErrorPrimitive; /* Number of times the phy received an ERROR primitive */ 2260 bit32 inboundCRCError; /* Number of inbound CRC Error */ 2261 bit32 codeViolation; /* Number of code violation */ 2262 } agsaPhyErrCounters_t; 2263 2264 2265 /** \brief 2266 * used in saGetPhyProfile 2267 */ 2268 typedef struct agsaPhyErrCountersPage_s 2269 { 2270 bit32 invalidDword; 2271 bit32 runningDisparityError; 2272 bit32 codeViolation; 2273 bit32 lossOfDwordSynch; 2274 bit32 phyResetProblem; 2275 bit32 inboundCRCError; 2276 } agsaPhyErrCountersPage_t; 2277 2278 /** \brief structure describes bandwidth counters of a PHY in the SAS/SATA 2279 * 2280 * Structure is used as a parameter passed in saGetPhyProfile() 2281 * to describe the error counter 2282 * 2283 */ 2284 2285 typedef struct agsaPhyBWCountersPage_s 2286 { 2287 bit32 TXBWCounter; 2288 bit32 RXBWCounter; 2289 } agsaPhyBWCountersPage_t; 2290 2291 2292 2293 /** \brief structure describe hardware configuration 2294 * 2295 * Structure is used as a parameter passed in saInitialize() to describe the 2296 * configuration used during hardware initialization 2297 * 2298 */ 2299 typedef struct agsaHwConfig_s 2300 { 2301 bit32 phyCount; /**< Number of PHYs that are to be configured 2302 and initialized. */ 2303 bit32 hwInterruptCoalescingTimer; /**< Host Interrupt CoalescingTimer */ 2304 bit32 hwInterruptCoalescingControl; /**< Host Interrupt CoalescingControl */ 2305 bit32 intReassertionOption; /**< Interrupt Ressertion Option */ 2306 bit32 hwOption; /** PCAD64 on 64 bit addressing */ 2307 2308 agsaPhyAnalogSetupTable_t phyAnalogConfig; /**< Phy Analog Setting Table */ 2309 } agsaHwConfig_t; 2310 2311 /** \brief structure describe software configuration 2312 * 2313 * Structure is used as a parameter passed in saInitialize() to describe the 2314 * configuration used during software initialization 2315 * 2316 */ 2317 typedef struct agsaSwConfig_s 2318 { 2319 bit32 maxActiveIOs; /**< Maximum active I/O requests supported */ 2320 bit32 numDevHandles; /**< Number of SAS/SATA device handles allocated 2321 in the pool */ 2322 bit32 smpReqTimeout; /**< SMP request time out in millisecond */ 2323 bit32 numberOfEventRegClients; /**< Maximum number of OS Layer clients for the event 2324 registration defined by saRegisterEventCallback() */ 2325 bit32 sizefEventLog1; /**< Size of Event Log 1 */ 2326 bit32 sizefEventLog2; /**< Size of Event Log 2 */ 2327 bit32 eventLog1Option; /**< Option of Event Log 1 */ 2328 bit32 eventLog2Option; /**< Option of Event Log 2 */ 2329 2330 bit32 fatalErrorInterruptEnable:1; /**< 0 Fatal Error Iterrupt Enable */ 2331 bit32 sgpioSupportEnable:1; /**< 1 SGPIO Support Enable */ 2332 bit32 fatalErrorInterruptVector:8; /**< 2-9 Fatal Error Interrupt Vector */ 2333 bit32 max_MSI_InterruptVectors:8; /**< 10-18 Maximum MSI Interrupt Vectors */ 2334 bit32 max_MSIX_InterruptVectors:8; /**< 18-25 Maximum MSIX Interrupt Vectors */ 2335 bit32 legacyInt_X:1; /**< 26 Support Legacy Interrupt */ 2336 bit32 hostDirectAccessSupport:1; /**< 27 Support HDA mode */ 2337 bit32 hostDirectAccessMode:2; /**< 28-29 HDA mode: 00b - HDA SoftReset, 01b - HDA Normal */ 2338 bit32 enableDIF:1; /**< 30 */ 2339 bit32 enableEncryption:1; /**< 31 */ 2340 #ifdef SA_CONFIG_MDFD_REGISTRY 2341 bit32 disableMDF; /*disable MDF*/ 2342 #endif 2343 bit32 param1; /**< parameter1 */ 2344 bit32 param2; /**< parameter2 */ 2345 void *param3; /**< parameter3 */ 2346 void *param4; /**< paramater4 */ 2347 bit32 stallUsec; 2348 bit32 FWConfig; 2349 bit32 PortRecoveryResetTimer; 2350 void *mpiContextTable; /** Pointer to a table that contains agsaMPIContext_t 2351 entries. This table is used to fill in MPI table 2352 fields. Values in this table are written to MPI table last. 2353 Any previous values in MPI table are overwritten by values 2354 in this table. */ 2355 2356 bit32 mpiContextTablelen; /** Number of agsaMPIContext_t entries in mpiContextTable */ 2357 2358 #if defined(SALLSDK_DEBUG) 2359 bit32 sallDebugLevel; /**< Low Layer debug level */ 2360 #endif 2361 2362 #ifdef SA_ENABLE_PCI_TRIGGER 2363 bit32 PCI_trigger; 2364 #endif /* SA_ENABLE_PCI_TRIGGER */ 2365 2366 #ifdef SA_ENABLE_TRACE_FUNCTIONS 2367 bit32 TraceDestination; 2368 bit32 TraceBufferSize; 2369 bit32 TraceMask; 2370 #endif /* SA_ENABLE_TRACE_FUNCTIONS */ 2371 } agsaSwConfig_t; 2372 2373 2374 typedef struct agsaQueueInbound_s 2375 { 2376 bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). 2377 A value of zero indicates that the host disabled this queue.*/ 2378 bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ 2379 bit32 priority:2; /* Queue priority: 2380 00: normal priority 2381 01: high priority 2382 10: reserved 2383 11: reserved */ 2384 bit32 reserved:30; 2385 } agsaQueueInbound_t; 2386 2387 typedef struct agsaQueueOutbound_s 2388 { 2389 bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). 2390 A value of zero indicates that the host disabled 2391 this queue.*/ 2392 bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ 2393 bit32 interruptDelay:16; /* Time, in usec, to delay interrupts to the host. 2394 Zero means not to delay based on time. An 2395 interrupt is passed to the host when either of 2396 the interruptDelay or interruptCount parameters 2397 is satisfied. Default value is 0.*/ 2398 bit32 interruptCount:16; /* Number of interrupts required before passing to 2399 the host. Zero means not to coalesce based on count. */ 2400 bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when 2401 Multiple Messages is enabled, this field is the 2402 index to the MSI vectors derived from a single 2403 Message Address and multiple Message Data. 2404 For MSI-X, this field is the index to the 2405 MSI-X Table Structure. */ 2406 bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling) 2407 1b: Interrupt enabled */ 2408 bit32 reserved:23; 2409 2410 } agsaQueueOutbound_t; 2411 2412 typedef struct agsaPhyCalibrationTbl_s 2413 { 2414 bit32 txPortConfig1; /* transmitter per port configuration 1 SAS_SATA G1 */ 2415 bit32 txPortConfig2; /* transmitter per port configuration 2 SAS_SATA G1*/ 2416 bit32 txPortConfig3; /* transmitter per port configuration 3 SAS_SATA G1*/ 2417 bit32 txConfig1; /* transmitter configuration 1 */ 2418 bit32 rvPortConfig1; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 2419 bit32 rvPortConfig2; /* reveiver per port configuration 2 SAS_SATA G3 */ 2420 bit32 rvConfig1; /* reveiver per configuration 1 */ 2421 bit32 rvConfig2; /* reveiver per configuration 2 */ 2422 bit32 reserved[2]; /* reserved */ 2423 } agsaPhyCalibrationTbl_t; 2424 2425 typedef struct agsaQueueConfig_s 2426 { 2427 bit16 numInboundQueues; 2428 bit16 numOutboundQueues; 2429 bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS]; 2430 bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS]; 2431 bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS]; 2432 bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS]; 2433 bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS]; 2434 bit8 iqNormalPriorityProcessingDepth; 2435 bit8 iqHighPriorityProcessingDepth; 2436 bit8 generalEventQueue; 2437 bit8 tgtDeviceRemovedEventQueue; 2438 bit32 queueOption; 2439 agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q]; 2440 agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q]; 2441 } agsaQueueConfig_t; 2442 2443 #define OQ_SHARE_PATH_BIT 0x00000001 2444 2445 typedef struct agsaFwImg_s 2446 { 2447 bit8 *aap1Img; /**< AAP1 Image */ 2448 bit32 aap1Len; /**< AAP1 Image Length */ 2449 bit8 *ilaImg; /**< ILA Image */ 2450 bit32 ilaLen; /**< ILA Image Length */ 2451 bit8 *iopImg; /**< IOP Image */ 2452 bit32 iopLen; /**< IOP Image Length */ 2453 bit8 *istrImg; /**< Init String */ 2454 bit32 istrLen; /**< Init String Length */ 2455 } agsaFwImg_t; 2456 2457 /** \brief generic memory descriptor 2458 * 2459 * a generic memory descriptor used for describing a memory requirement in a structure 2460 * 2461 */ 2462 typedef struct agsaMem_s 2463 { 2464 void *virtPtr; /**< Virtual pointer to the memory chunk */ 2465 void *osHandle; /**< Handle used for OS to free memory */ 2466 bit32 phyAddrUpper; /**< Upper 32 bits of physical address */ 2467 bit32 phyAddrLower; /**< Lower 32 bits of physical address */ 2468 bit32 totalLength; /**< Total length in bytes allocated */ 2469 bit32 numElements; /**< Number of elements */ 2470 bit32 singleElementLength; /**< Size in bytes of an element */ 2471 bit32 alignment; /**< Alignment in bytes needed. A value of one indicates 2472 no specific alignment requirement */ 2473 bit32 type; /**< DMA or Cache */ 2474 bit32 reserved; /**< reserved */ 2475 } agsaMem_t; 2476 2477 /** \brief specify the controller Event Log for the SAS/SATA LL Layer 2478 * 2479 * data structure used in the saGetControllerEventLogInfo() function calls 2480 * 2481 */ 2482 typedef struct agsaControllerEventLog_s 2483 { 2484 agsaMem_t eventLog1; 2485 agsaMem_t eventLog2; 2486 bit32 eventLog1Option; 2487 bit32 eventLog2Option; 2488 } agsaControllerEventLog_t; 2489 2490 /* Log Option - bit3-0 */ 2491 #define DISABLE_LOGGING 0x0 2492 #define CRITICAL_ERROR 0x1 2493 #define WARNING 0x2 2494 #define NOTICE 0x3 2495 #define INFORMATION 0x4 2496 #define DEBUGGING 0x5 2497 2498 /** \brief specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer 2499 * 2500 * data structure used in the saGetRequirements() and the saInitialize() function calls 2501 * 2502 */ 2503 typedef struct agsaSASDiagExecute_s 2504 { 2505 bit32 command; 2506 bit32 param0; 2507 bit32 param1; 2508 bit32 param2; 2509 bit32 param3; 2510 bit32 param4; 2511 bit32 param5; 2512 } agsaSASDiagExecute_t; 2513 2514 2515 /** \brief for the SAS/SATA LL Layer 2516 * 2517 * This data structure contains the general status of a SAS Phy. 2518 * Section 4.60 2519 */ 2520 typedef struct agsaSASPhyGeneralStatusPage_s 2521 { 2522 bit32 Dword0; 2523 bit32 Dword1; 2524 } agsaSASPhyGeneralStatusPage_t; 2525 2526 2527 /** \brief specify the memory allocation requirement for the SAS/SATA LL Layer 2528 * 2529 * data structure used in the saGetRequirements() and the saInitialize() function calls 2530 * 2531 */ 2532 typedef struct agsaMemoryRequirement_s 2533 { 2534 bit32 count; /**< The number of memory chunks used 2535 in the agMemory table */ 2536 agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS]; /**< The structure that defines the memory 2537 requirement structure */ 2538 } agsaMemoryRequirement_t; 2539 2540 2541 /** \brief describe a SAS address and PHY Identifier 2542 * 2543 * This structure is used 2544 * 2545 */ 2546 typedef struct agsaSASAddressID_s 2547 { 2548 bit8 sasAddressLo[4]; /**< HOST SAS address lower part */ 2549 bit8 sasAddressHi[4]; /**< HOST SAS address higher part */ 2550 bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */ 2551 } agsaSASAddressID_t; 2552 2553 /** \brief data structure provides some information about a SATA device 2554 * 2555 * data structure provides some information about a SATA device discovered 2556 * following the SATA discovery. 2557 * 2558 */ 2559 typedef struct agsaDeviceInfo_s 2560 { 2561 bit16 smpTimeout; 2562 bit16 it_NexusTimeout; 2563 bit16 firstBurstSize; 2564 bit8 reserved; 2565 /* Not Used */ 2566 bit8 devType_S_Rate; 2567 /* Bit 6-7: reserved 2568 Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device 2569 00: STP device 2570 01: SSP or SMP device 2571 10: Direct SATA device 2572 Bit 0-3: Connection Rate field when opening the device. 2573 Code Description: 2574 08h: 1.5 Gbps 2575 09h: 3.0 Gbps 2576 0ah: 6.0 Gbps 2577 All others Reserved 2578 */ 2579 bit8 sasAddressHi[4]; 2580 bit8 sasAddressLo[4]; 2581 bit32 flag; 2582 /* 2583 flag 2584 Bit 0: Retry flag. 2585 1b: enable SAS TLR (Transport Layer Retry). 2586 0b: disable SAS TLR (Transport Layer Retry). 2587 When used during device registration, it is recommended that TLR is 2588 enabled, i.e. set the bit to 1. 2589 Bit 1: Priority setting for AWT (Arbitration Wait Time) for this device. 2590 0b: Default setting (recommended). Actual AWT value TBD. 2591 1b: Increase priority. Actual AWT value TBD. 2592 Bit 2-3: Reserved 2593 Bit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set to 10b 2594 which indicates a directly-attached SATA drive. 2595 Bit 12-15: Reserved 2596 Bit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that 2597 can be established with the device concurrently. This field is set to the lowest port width along the pathway 2598 from the controller to the device. This is applicable only to the SPCv controller. 2599 However, for backward compatibility reasons, if this field is set to zero, it is treated as 1 so that the controller 2600 can establish at least one connection. 2601 Bit 20: Initiator Role 2602 This bit indicates whether the device has SSP initiator role capability. This is applicable only to the SPCv controller. 2603 0b : The device has no SSP initiator capability. 2604 1b : The device has SSP initiator capability. 2605 Bit 21: ATAPI Device Flag. (Only applies to the SPCv) Flag to indicate ATAPI protocol support 2606 0b : Device does not support ATAPI protocol. 2607 1b : Device supports ATAPI protocol. 2608 Bit 22-31: Reserved 2609 */ 2610 } agsaDeviceInfo_t; 2611 2612 2613 #define DEV_INFO_MASK 0xFF 2614 #define DEV_INFO_MCN_SHIFT 16 2615 #define DEV_INFO_IR_SHIFT 20 2616 2617 #define RETRY_DEVICE_FLAG (1 << SHIFT0) 2618 #define AWT_DEVICE_FLAG (1 << SHIFT1) 2619 #define SSP_DEVICE_FLAG (1 << SHIFT20) 2620 #define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */ 2621 #define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22) 2622 2623 2624 #define DEV_LINK_RATE 0x3F 2625 2626 #define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ 2627 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) 2628 2629 #define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ 2630 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) 2631 2632 #define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \ 2633 (((devInfo)->devType_S_Rate & 0xC0) >> 5) 2634 2635 #define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ 2636 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) 2637 2638 #define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ 2639 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) 2640 2641 /** \brief data structure provides some information about a SATA device 2642 * 2643 * data structure provides some information about a SATA device discovered 2644 * following the SATA discovery. 2645 * 2646 */ 2647 typedef struct agsaSATADeviceInfo_s 2648 { 2649 agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the 2650 SAS/SATA device information */ 2651 bit8 connection; /**< How device is connected: 2652 0: Direct attached. 2653 1: Behind Port Multiplier, 2654 portMultiplierField is valid. 2655 2: STP, stpPhyIdentifier is valid */ 2656 2657 bit8 portMultiplierField; /**< The first 4 bits indicate that 2658 the Port Multiplier field is defined 2659 by SATA-II. This field is valid only 2660 if the connection field above is 2661 set to 1 */ 2662 2663 bit8 stpPhyIdentifier; /**< PHY ID of the STP PHY. Valid only if 2664 connection field is set to 2 (STP). */ 2665 2666 bit8 reserved; 2667 bit8 signature[8]; /**< The signature of SATA in Task 2668 File registers following power up. 2669 Only five bytes are defined by ATA. 2670 The added three bytes are for 2671 alignment purposes */ 2672 } agsaSATADeviceInfo_t; 2673 2674 /** \brief data structure provides some information about a SAS device 2675 * 2676 * data structure provides some information about a SAS device discovered 2677 * following the SAS discovery 2678 * 2679 */ 2680 typedef struct agsaSASDeviceInfo_s 2681 { 2682 agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the SAS/SATA 2683 device information */ 2684 bit8 initiator_ssp_stp_smp; /**< SAS initiator capabilities */ 2685 /* b4-7: reserved */ 2686 /* b3: SSP initiator port */ 2687 /* b2: STP initiator port */ 2688 /* b1: SMP initiator port */ 2689 /* b0: reserved */ 2690 bit8 target_ssp_stp_smp; /**< SAS target capabilities */ 2691 /* b4-7: reserved */ 2692 /* b3: SSP target port */ 2693 /* b2: STP target port */ 2694 /* b1: SMP target port */ 2695 /* b0: reserved */ 2696 bit32 numOfPhys; /**< Number of PHYs in the device */ 2697 bit8 phyIdentifier; /**< PHY IDENTIFIER in IDENTIFY address 2698 frame as defined by the SAS 2699 specification. */ 2700 } agsaSASDeviceInfo_t; 2701 2702 #define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT /* SSP Initiator port */ 2703 #define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT /* STP Initiator port */ 2704 #define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT /* SMP Initiator port */ 2705 #define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT /* SATA device, valid in the discovery response only */ 2706 2707 #define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \ 2708 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) 2709 2710 #define SA_SASDEV_IS_STP_INITIATOR(sasDev) \ 2711 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) 2712 2713 #define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \ 2714 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) 2715 2716 #define SA_SASDEV_IS_SSP_TARGET(sasDev) \ 2717 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) 2718 2719 #define SA_SASDEV_IS_STP_TARGET(sasDev) \ 2720 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) 2721 2722 #define SA_SASDEV_IS_SMP_TARGET(sasDev) \ 2723 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) 2724 2725 #define SA_SASDEV_IS_SATA_DEVICE(sasDev) \ 2726 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT) 2727 2728 2729 2730 2731 /** \brief the data structure describe SG list 2732 * 2733 * the data structure describe SG list 2734 * 2735 */ 2736 typedef struct _SASG_DESCRIPTOR 2737 { 2738 bit32 sgLower; /**< Lower 32 bits of data area physical address */ 2739 bit32 sgUpper; /**< Upper 32 bits of data area physical address */ 2740 bit32 len; /**< Total data length in bytes */ 2741 } SASG_DESCRIPTOR, * PSASG_DESCRIPTOR; 2742 2743 /** \brief data structure used to pass information about the scatter-gather list to the LL Layer 2744 * 2745 * The ESGL pages are uncached, have a configurable number of SGL 2746 * of (min, max) = (1, 10), and are 16-byte aligned. Although 2747 * the application can configure the page size, the size must be 2748 * incremented in TBD-byte increments. Refer the hardware 2749 * documentation for more detail on the format of ESGL 2750 * structure. 2751 * 2752 */ 2753 typedef struct agsaSgl_s 2754 { 2755 bit32 sgLower; /**< Lower 32 bits of data area physical address */ 2756 bit32 sgUpper; /**< Upper 32 bits of data area physical address */ 2757 bit32 len; /**< Total data length in bytes */ 2758 bit32 extReserved; /**< bit31 is for extended sgl list */ 2759 } agsaSgl_t; 2760 2761 /** \brief data structure is used to pass information about the extended 2762 * scatter-gather list (ESGL) to the LL Layer 2763 * 2764 * The agsaEsgl_t data structure is used to pass information about the 2765 * extended scatter-gather list (ESGL) to the LL Layer. 2766 * 2767 * When ESGL is used, its starting address is specified the first descriptor 2768 * entry (i.e. descriptor[0]) in agsaSgl_t structure. 2769 * 2770 * The ESGL pages are uncached, have a fixed number of SGL of 10, and are 2771 * 16-byte aligned. Refer the hardware documentation for more 2772 * detail on ESGL. 2773 * 2774 */ 2775 typedef struct agsaEsgl_s 2776 { 2777 agsaSgl_t descriptor[MAX_ESGL_ENTRIES]; 2778 } agsaEsgl_t; 2779 2780 /** \brief data structure describes an SSP Command INFORMATION UNIT 2781 * 2782 * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of 2783 * the SSP frame. 2784 * 2785 * Currently, Additional CDB length is supported to 16 bytes 2786 * 2787 */ 2788 #define MAX_CDB_LEN 32 2789 typedef struct agsaSSPCmdInfoUnitExt_s 2790 { 2791 bit8 lun[8]; 2792 bit8 reserved1; 2793 bit8 efb_tp_taskAttribute; 2794 bit8 reserved2; 2795 bit8 additionalCdbLen; 2796 bit8 cdb[MAX_CDB_LEN]; 2797 } agsaSSPCmdInfoUnitExt_t ; 2798 2799 #define DIF_UDT_SIZE 6 2800 2801 /* difAction in agsaDif_t */ 2802 #define AGSA_DIF_INSERT 0 2803 #define AGSA_DIF_VERIFY_FORWARD 1 2804 #define AGSA_DIF_VERIFY_DELETE 2 2805 #define AGSA_DIF_VERIFY_REPLACE 3 2806 #define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5 2807 #define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7 2808 2809 #define agsaDIFSectorSize512 0 2810 #define agsaDIFSectorSize520 1 2811 #define agsaDIFSectorSize4096 2 2812 #define agsaDIFSectorSize4160 3 2813 2814 2815 2816 typedef struct agsaDif_s 2817 { 2818 agBOOLEAN enableDIFPerLA; 2819 bit32 flags; 2820 bit16 initialIOSeed; 2821 bit16 reserved; 2822 bit32 DIFPerLAAddrLo; 2823 bit32 DIFPerLAAddrHi; 2824 bit16 DIFPerLARegion0SecCount; 2825 bit16 Reserved2; 2826 bit8 udtArray[DIF_UDT_SIZE]; 2827 bit8 udrtArray[DIF_UDT_SIZE]; 2828 } agsaDif_t; 2829 2830 2831 /* From LL SDK2 */ 2832 #define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/ 2833 #define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */ 2834 #define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */ 2835 #define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */ 2836 #define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */ 2837 #define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */ 2838 #define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */ 2839 #define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */ 2840 #define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/ 2841 #define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */ 2842 #define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/ 2843 #define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */ 2844 #define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16 2845 #define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */ 2846 #define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */ 2847 #define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */ 2848 #define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */ 2849 #define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */ 2850 #define DIF_FLAG_BITS_UDTV_SHIFT 20 2851 #define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */ 2852 #define DIF_FLAG_BITS_UDTUPSHIFT 26 2853 2854 typedef struct agsaEncryptDek_s 2855 { 2856 bit32 dekTable; 2857 bit32 dekIndex; 2858 } agsaEncryptDek_t; 2859 2860 typedef struct agsaEncrypt_s 2861 { 2862 agsaEncryptDek_t dekInfo; 2863 bit32 kekIndex; 2864 agBOOLEAN keyTagCheck; 2865 agBOOLEAN enableEncryptionPerLA; /* new */ 2866 bit32 sectorSizeIndex; 2867 bit32 cipherMode; 2868 bit32 keyTag_W0; 2869 bit32 keyTag_W1; 2870 bit32 tweakVal_W0; 2871 bit32 tweakVal_W1; 2872 bit32 tweakVal_W2; 2873 bit32 tweakVal_W3; 2874 bit32 EncryptionPerLAAddrLo; /* new */ 2875 bit32 EncryptionPerLAAddrHi; /* new */ 2876 bit16 EncryptionPerLRegion0SecCount; /* new */ 2877 bit16 reserved; 2878 } agsaEncrypt_t; 2879 2880 /** \brief data structure describes a SAS SSP command request to be sent to the target device 2881 * 2882 * data structure describes a SAS SSP command request to be sent to the 2883 * target device. This structure limits the CDB length in SSP 2884 * command up to 16 bytes long. 2885 * 2886 * This data structure is one instance of the generic request issued to 2887 * saSSPStart() and is passed as an agsaSASRequestBody_t . 2888 * 2889 */ 2890 typedef struct agsaSSPInitiatorRequest_s 2891 { 2892 agsaSgl_t agSgl; /**< This structure is used to define either 2893 an ESGL list or a single SGL for the SSP 2894 command operation */ 2895 bit32 dataLength; /**< Total data length in bytes */ 2896 bit16 firstBurstSize; /**< First Burst Size field as defined by 2897 SAS specification */ 2898 bit16 flag; /**< bit1-0 TLR as SAS specification 2899 bit31-2 reserved */ 2900 agsaSSPCmdInfoUnit_t sspCmdIU; /**< Structure containing SSP Command 2901 INFORMATION UNIT */ 2902 agsaDif_t dif; 2903 agsaEncrypt_t encrypt; 2904 #ifdef SA_TESTBASE_EXTRA 2905 /* Added by TestBase */ 2906 bit16 bstIndex; 2907 #endif /* SA_TESTBASE_EXTRA */ 2908 } agsaSSPInitiatorRequest_t; 2909 2910 /** \brief data structure describes a SAS SSP command request Ext to be sent to the target device 2911 * 2912 * data structure describes a SAS SSP command request to be sent to the 2913 * target device. This structure support the CDB length in SSP 2914 * command more than 16 bytes long. 2915 * 2916 * This data structure is one instance of the generic request issued to 2917 * saSSPStart() and is passed as an agsaSASRequestBody_t . 2918 * 2919 */ 2920 typedef struct agsaSSPInitiatorRequestExt_s 2921 { 2922 agsaSgl_t agSgl; /**< This structure is used to define either 2923 an ESGL list or a single SGL for the SSP 2924 command operation */ 2925 bit32 dataLength; 2926 bit16 firstBurstSize; 2927 bit16 flag; 2928 agsaSSPCmdInfoUnitExt_t sspCmdIUExt; 2929 agsaDif_t dif; 2930 agsaEncrypt_t encrypt; 2931 } agsaSSPInitiatorRequestExt_t; 2932 2933 2934 typedef struct agsaSSPInitiatorRequestIndirect_s 2935 { 2936 agsaSgl_t agSgl; /**< This structure is used to define either 2937 an ESGL list or a single SGL for the SSP 2938 command operation */ 2939 bit32 dataLength; 2940 bit16 firstBurstSize; 2941 bit16 flag; 2942 bit32 sspInitiatorReqAddrUpper32; /**< The upper 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ 2943 bit32 sspInitiatorReqAddrLower32; /**< The lower 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ 2944 bit32 sspInitiatorReqLen; /**< Specifies the length of the SSP initiator request in bytes */ 2945 agsaDif_t dif; 2946 agsaEncrypt_t encrypt; 2947 2948 }agsaSSPInitiatorRequestIndirect_t; 2949 2950 2951 2952 2953 /** \brief data structure describes a SAS SSP target read and write request 2954 * 2955 * The agsaSSPTargetRequest_t data structure describes a SAS SSP target read 2956 * and write request to be issued on the port. It includes the 2957 * length of the data to be received or sent, an offset into the 2958 * data block where the transfer is to start, and a list of 2959 * scatter-gather buffers. 2960 * 2961 * This data structure is one instance of the generic request issued 2962 * to saSSPStart() and is passed as an agsaSASRequestBody_t . 2963 * 2964 */ 2965 /** bit definitions for sspOption 2966 Bit 0-1: Transport Layer Retry setting for other phase: 2967 00b: No retry 2968 01b: Retry on ACK/NAK timeout 2969 10b: Retry on NAK received 2970 11b: Retry on both ACK/NAK timeout and NAK received 2971 Bit 2-3: Transport Layer Retry setting for data phase: 2972 00b: No retry 2973 01b: Retry on ACK/NAK timeout 2974 10b: Retry on NAK received 2975 11b: Retry on both ACK/NAK timeout and NAK received 2976 Bit 4: Retry Data Frame. Valid only on write command. Indicates whether Target supports RTL for this particular IO. 2977 1b: enabled 2978 0b: disabled 2979 Bit 5: Auto good response on successful read (data transfer from target to initiator) request. 2980 1b: Enabled 2981 0b: Disabled 2982 Bits 6-15 : Reserved. 2983 */ 2984 typedef struct agsaSSPTargetRequest_s 2985 { 2986 agsaSgl_t agSgl; /**< This structure is used to define either an ESGL list or 2987 a single SGL for the target read or write operation */ 2988 bit32 dataLength; /**< Specifies the amount of data to be sent in this data phase */ 2989 bit32 offset; /**< Specifies the offset into the overall data block 2990 where this data phase is to begin */ 2991 bit16 agTag; /**< Tag from ossaSSPReqReceived(). */ 2992 bit16 sspOption; /**< SSP option for retry */ 2993 agsaDif_t dif; 2994 } agsaSSPTargetRequest_t; 2995 2996 #define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */ 2997 #define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */ 2998 2999 #define SSP_OPTION_OTHR_NO_RETRY 0 3000 #define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1 3001 #define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2 3002 #define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 3003 3004 #define SSP_OPTION_DATA_NO_RETRY 0 3005 #define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1 3006 #define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2 3007 #define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 3008 3009 #define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4) 3010 #define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5) 3011 #define SSP_OPTION_ENCRYPT (1 << SHIFT6) 3012 #define SSP_OPTION_DIF (1 << SHIFT7) 3013 #define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15) 3014 3015 3016 /** \brief data structure describes a SAS SSP target response to be issued 3017 * on the port 3018 * 3019 * This data structure is one instance of the generic request issued to 3020 * saSSPStart() and is passed as an agsaSASRequestBody_t 3021 * 3022 */ 3023 typedef struct agsaSSPTargetResponse_s 3024 { 3025 bit32 agTag; /**< Tag from ossaSSPReqReceived(). */ 3026 void *frameBuf; 3027 bit32 respBufLength; /**< Specifies the length of the Response buffer */ 3028 bit32 respBufUpper; /**< Upper 32 bit of physical address of OS Layer 3029 allocated the Response buffer 3030 (agsaSSPResponseInfoUnit_t). 3031 Valid only when respBufLength is not zero */ 3032 bit32 respBufLower; /**< Lower 32 bit of physical address of OS Layer 3033 allocated the Response buffer 3034 (agsaSSPResponseInfoUnit_t). 3035 Valid only when respBufLength is not zero */ 3036 bit32 respOption; /**< Bit 0-1: ACK and NAK retry option: 3037 00b: No retry 3038 01b: Retry on ACK/NAK timeout 3039 10b: Retry on NAK received 3040 11b: Retry on both ACK/NAK timeout and NAK received */ 3041 } agsaSSPTargetResponse_t; 3042 3043 #define RESP_OPTION_BITS 0x3 /** bit0-1 */ 3044 #define RESP_OPTION_ODS 0x8000 /** bit15 */ 3045 3046 /** \brief data structure describes a SMP request or response frame to be sent on the SAS port 3047 * 3048 * The agsaSMPFrame_t data structure describes a SMP request or response 3049 * frame to be issued or sent on the SAS port. 3050 * 3051 * This data structure is one instance of the generic request issued to 3052 * saSMPStart() and is passed as an agsaSASRequestBody_t . 3053 * 3054 */ 3055 typedef struct agsaSMPFrame_s 3056 { 3057 void *outFrameBuf; /**< if payload is less than 32 bytes,A virtual 3058 frameBuf can be used. instead of physical 3059 address. Set to NULL and use physical 3060 address if payload is > 32 bytes */ 3061 bit32 outFrameAddrUpper32; /**< The upper 32 bits of the 64-bit physical 3062 DMA address of the SMP frame buffer */ 3063 bit32 outFrameAddrLower32; /**< The lower 32 bits of the 64-bit physical 3064 DMA address of the SMP frame buffer */ 3065 bit32 outFrameLen; /**< Specifies the length of the SMP request 3066 frame excluding the CRC field in bytes */ 3067 bit32 inFrameAddrUpper32; /**< The upper 32 bits of the 64-bit phsical address 3068 of DMA address of response SMP Frame buffer */ 3069 bit32 inFrameAddrLower32; /**< The lower 32 bits of the 64-bit phsical address 3070 of DMA address of response SMP Frame buffer */ 3071 bit32 inFrameLen; /**< Specifies the length of the SMP response 3072 frame excluding the CRC field in bytes */ 3073 bit32 expectedRespLen; /**< Specifies the length of SMP Response */ 3074 bit32 flag; /** For the SPCv controller: 3075 Bit 0: Indirect Response (IR). This indicates 3076 direct or indirect mode for SMP response frame 3077 to be received. 3078 0b: Direct mode 3079 1b: Indirect mode 3080 3081 Bit 1: Indirect Payload (IP). This indicates 3082 direct or indirect mode for SMP request frame 3083 to be sent. 3084 0b: Direct mode 3085 1b: Indirect mode 3086 3087 Bits 2-31: Reserved 3088 For the SPC controller: This is not applicable. 3089 */ 3090 3091 } agsaSMPFrame_t; 3092 3093 #define smpFrameFlagDirectResponse 0 3094 #define smpFrameFlagIndirectResponse 1 3095 #define smpFrameFlagDirectPayload 0 3096 #define smpFrameFlagIndirectPayload 2 3097 3098 /** \brief union data structure specifies a request 3099 * 3100 * union data structure specifies a request 3101 */ 3102 typedef union agsaSASRequestBody_u 3103 { 3104 agsaSSPInitiatorRequest_t sspInitiatorReq; /**< Structure containing the SSP initiator request, Support up to 16 bytes CDB */ 3105 agsaSSPInitiatorRequestExt_t sspInitiatorReqExt; /**< Structure containing the SSP initiator request for CDB > 16 bytes */ 3106 agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect; /**< Structure containing the SSP indirect initiator request */ 3107 agsaSSPTargetRequest_t sspTargetReq; /**< Structure containing the SSP Target request */ 3108 agsaSSPScsiTaskMgntReq_t sspTaskMgntReq; /**< Structure containing the SSP SCSI Task Management request */ 3109 agsaSSPTargetResponse_t sspTargetResponse; /**< Structure containing the SSP Target response. */ 3110 agsaSMPFrame_t smpFrame; /**< Structure containing SMP request or response frame */ 3111 }agsaSASRequestBody_t; 3112 3113 3114 3115 3116 /** \brief data structure describes an STP or direct connect SATA command 3117 * 3118 * The agsaSATAInitiatorRequest_t data structure describes an STP or direct 3119 * connect SATA command request to be sent to the device and 3120 * passed as a parameter to saSATAStart() function. 3121 * 3122 * This structure is an encapsulation of SATA FIS (Frame Information 3123 * Structures), which enables the execution of ATA command 3124 * descriptor using SATA transport 3125 * 3126 */ 3127 typedef struct agsaSATAInitiatorRequest_s 3128 { 3129 agsaSgl_t agSgl; /**< This structure is used to define either an ESGL 3130 list or a single SGL for operation that involves 3131 DMA transfer */ 3132 3133 bit32 dataLength; /**< Total data length in bytes */ 3134 3135 bit32 option; /**< Operational option, defined using the bit field. 3136 b7-1: reserved 3137 b0: AGSA-STP-CLOSE-CLEAR-AFFILIATION */ 3138 3139 agsaSATAHostFis_t fis; /**< The FIS request */ 3140 agsaDif_t dif; 3141 agsaEncrypt_t encrypt; 3142 bit8 scsiCDB[16]; 3143 #ifdef SA_TESTBASE_EXTRA 3144 /* Added by TestBase */ 3145 bit16 bstIndex; 3146 #endif /* SA_TESTBASE_EXTRA */ 3147 } agsaSATAInitiatorRequest_t; 3148 3149 3150 /* controller Configuration page */ 3151 #define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04 3152 #define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05 3153 #define AGSA_IO_GENERAL_CONFIG_PAGE 0x06 3154 #define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20 3155 #define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21 3156 #define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22 3157 #define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23 3158 3159 #ifdef HIALEAH_ENCRYPTION 3160 typedef struct agsaEncryptGeneralPage_s { 3161 bit32 numberOfKeksPageCode; /* 0x20 */ 3162 bit32 KeyCardIdKekIndex; 3163 bit32 KeyCardId3_0; 3164 bit32 KeyCardId7_4; 3165 bit32 KeyCardId11_8; 3166 } agsaEncryptGeneralPage_t; 3167 #else 3168 typedef struct agsaEncryptGeneralPage_s { 3169 bit32 pageCode; /* 0x20 */ 3170 bit32 numberOfDeks; 3171 } agsaEncryptGeneralPage_t; 3172 #endif /* HIALEAH_ENCRYPTION */ 3173 3174 #define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00 3175 #define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8 3176 3177 /* sTSDK 4.14 */ 3178 typedef struct agsaEncryptDekConfigPage_s { 3179 bit32 pageCode; 3180 bit32 table0AddrLo; 3181 bit32 table0AddrHi; 3182 bit32 table0Entries; 3183 bit32 table0BFES; 3184 bit32 table1AddrLo; 3185 bit32 table1AddrHi; 3186 bit32 table1Entries; 3187 bit32 table1BFES; 3188 } agsaEncryptDekConfigPage_t; 3189 3190 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000 3191 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28 3192 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000 3193 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24 3194 3195 /*sTSDK 4.18 */ 3196 /* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */ 3197 /* NAR, CORCAP and USRCAP are valid only when AUT==1 */ 3198 typedef struct agsaEncryptControlParamPage_s { 3199 bit32 pageCode; /* 0x22 */ 3200 bit32 CORCAP; /* Crypto Officer Role Capabilities */ 3201 bit32 USRCAP; /* User Role Capabilities */ 3202 bit32 CCS; /* Current Crypto Services */ 3203 bit32 NOPR; /* Number of Operators */ 3204 } agsaEncryptControlParamPage_t; 3205 3206 typedef struct agsaEncryptInfo_s { 3207 bit32 encryptionCipherMode; 3208 bit32 encryptionSecurityMode; 3209 bit32 status; 3210 bit32 flag; 3211 } agsaEncryptInfo_t; 3212 3213 3214 #define OperatorAuthenticationEnable_AUT 1 3215 #define ReturnToFactoryMode_ARF 2 3216 3217 /*sTSDK 4.19 */ 3218 typedef struct agsaEncryptSelfTestBitMap_s { 3219 bit32 AES_Test; 3220 bit32 KEY_WRAP_Test; 3221 bit32 HMAC_Test; 3222 } agsaEncryptSelfTestBitMap_t; 3223 3224 typedef struct agsaEncryptSelfTestStatusBitMap_s{ 3225 bit32 AES_Status; 3226 bit32 KEY_WRAP_Status; 3227 bit32 HMAC_Status; 3228 } agsaEncryptSelfTestStatusBitMap_t; 3229 3230 typedef struct agsaEncryptHMACTestDescriptor_s 3231 { 3232 bit32 Dword0; 3233 bit32 MsgAddrLo; 3234 bit32 MsgAddrHi; 3235 bit32 MsgLen; 3236 bit32 DigestAddrLo; 3237 bit32 DigestAddrHi; 3238 bit32 KeyAddrLo; 3239 bit32 KeyAddrHi; 3240 bit32 KeyLen; 3241 } agsaEncryptHMACTestDescriptor_t; 3242 3243 typedef struct agsaEncryptHMACTestResult_s 3244 { 3245 bit32 Dword0; 3246 bit32 Dword[12]; 3247 } agsaEncryptHMACTestResult_t; 3248 3249 typedef struct agsaEncryptSHATestDescriptor_s 3250 { 3251 bit32 Dword0; 3252 bit32 MsgAddrLo; 3253 bit32 MsgAddrHi; 3254 bit32 MsgLen; 3255 bit32 DigestAddrLo; 3256 bit32 DigestAddrHi; 3257 } agsaEncryptSHATestDescriptor_t; 3258 3259 typedef struct agsaEncryptSHATestResult_s 3260 { 3261 bit32 Dword0; 3262 bit32 Dword[12]; 3263 } agsaEncryptSHATestResult_t; 3264 3265 /* types of self test */ 3266 #define AGSA_BIST_TEST 0x1 3267 #define AGSA_HMAC_TEST 0x2 3268 #define AGSA_SHA_TEST 0x3 3269 3270 3271 /*sTSDK 4.13 */ 3272 typedef struct agsaEncryptDekBlob_s { 3273 bit8 dekBlob[80]; 3274 } agsaEncryptDekBlob_t; 3275 3276 typedef struct agsaEncryptKekBlob_s { 3277 bit8 kekBlob[48]; 3278 } agsaEncryptKekBlob_t; 3279 3280 /*sTSDK 4.45 */ 3281 typedef struct agsaEncryptHMACConfigPage_s 3282 { 3283 bit32 PageCode; 3284 bit32 CustomerTag; 3285 bit32 KeyAddrLo; 3286 bit32 KeyAddrHi; 3287 } agsaEncryptHMACConfigPage_t; 3288 3289 /*sTSDK 4.38 */ 3290 #define AGSA_ID_SIZE 31 3291 typedef struct agsaID_s { 3292 bit8 ID[AGSA_ID_SIZE]; 3293 }agsaID_t; 3294 3295 3296 #define SA_OPR_MGMNT_FLAG_MASK 0x00003000 3297 #define SA_OPR_MGMNT_FLAG_SHIFT 12 3298 3299 /* */ 3300 typedef struct agsaSASPhyMiscPage_s { 3301 bit32 Dword0; 3302 bit32 Dword1; 3303 } agsaSASPhyMiscPage_t ; 3304 3305 3306 typedef struct agsaHWEventEncrypt_s { 3307 bit32 encryptOperation; 3308 bit32 status; 3309 bit32 eq; /* error qualifier */ 3310 bit32 info; 3311 void *handle; 3312 void *param; 3313 } agsaHWEventEncrypt_t; 3314 3315 /*sTSDK 4.32 */ 3316 typedef struct agsaHWEventMode_s { 3317 bit32 modePageOperation; 3318 bit32 status; 3319 bit32 modePageLen; 3320 void *modePage; 3321 void *context; 3322 } agsaHWEventMode_t; 3323 3324 /*sTSDK 4.33 */ 3325 typedef struct agsaInterruptConfigPage_s { 3326 bit32 pageCode; 3327 bit32 vectorMask0; 3328 bit32 vectorMask1; 3329 bit32 ICTC0; 3330 bit32 ICTC1; 3331 bit32 ICTC2; 3332 bit32 ICTC3; 3333 bit32 ICTC4; 3334 bit32 ICTC5; 3335 bit32 ICTC6; 3336 bit32 ICTC7; 3337 } agsaInterruptConfigPage_t; 3338 typedef struct agsaIoGeneralPage_s { 3339 bit32 pageCode; /* 0x06 */ 3340 bit32 ActiveMask; 3341 bit32 QrntTime; 3342 } agsaIoGeneralPage_t; 3343 3344 /* \brief data structure defines detail information about Agilent Error 3345 * Detection Code (DIF) errors. 3346 * 3347 * The agsaDifDetails_t data structure defines detail information about 3348 * PMC Error Detection Code (DIF) error. Please refer to the latest T10 SBC 3349 * and SPC draft/specification for the definition of the Protection 3350 * Information. 3351 * 3352 * This structure is filled by the function saGetDifErrorDetails(). 3353 */ 3354 3355 typedef struct agsaDifDetails_s { 3356 bit32 UpperLBA; 3357 bit32 LowerLBA; 3358 bit8 sasAddressHi[4]; 3359 bit8 sasAddressLo[4]; 3360 bit32 ExpectedCRCUDT01; 3361 bit32 ExpectedUDT2345; 3362 bit32 ActualCRCUDT01; 3363 bit32 ActualUDT2345; 3364 bit32 DIFErrDevID; 3365 bit32 ErrBoffsetEDataLen; 3366 void * frame; 3367 } agsaDifDetails_t; 3368 3369 /** \brief data structure for SAS protocol timer configuration page. 3370 * 3371 */ 3372 typedef struct agsaSASProtocolTimerConfigurationPage_s{ 3373 bit32 pageCode; /* 0 */ 3374 bit32 MST_MSI; /* 1 */ 3375 bit32 STP_SSP_MCT_TMO; /* 2 */ 3376 bit32 STP_FRM_TMO; /* 3 */ 3377 bit32 STP_IDLE_TMO; /* 4 */ 3378 bit32 OPNRJT_RTRY_INTVL; /* 5 */ 3379 bit32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */ 3380 bit32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */ 3381 bit32 MAX_AIP; /* 8 */ 3382 } agsaSASProtocolTimerConfigurationPage_t; 3383 3384 3385 /** \brief data structure for firmware flash update saFwFlashUpdate(). 3386 * 3387 * The agsaUpdateFwFlash data structure specifies a request to saFwFlashUpdate() 3388 */ 3389 typedef struct agsaUpdateFwFlash_s 3390 { 3391 bit32 currentImageOffset; 3392 bit32 currentImageLen; 3393 bit32 totalImageLen; 3394 agsaSgl_t agSgl; 3395 } agsaUpdateFwFlash_t; 3396 3397 3398 3399 /** \brief data structure for extended firmware flash update saFwFlashExtUpdate(). 3400 * 3401 * The agsaFlashExtExecute_s data structure specifies a request to saFwFlashExtUpdate() 3402 */ 3403 typedef struct agsaFlashExtExecute_s 3404 { 3405 bit32 command; 3406 bit32 partOffset; 3407 bit32 dataLen; 3408 agsaSgl_t *agSgl; 3409 } agsaFlashExtExecute_t; 3410 3411 3412 /** \brief data structure for firmware flash update saFwFlashUpdate(). 3413 * 3414 * The agsaFlashExtResponse_t data structure specifies a request to ossaFlashExtExecuteCB().() 3415 */ 3416 typedef struct agsaFlashExtResponse_s 3417 { 3418 bit32 epart_size; 3419 bit32 epart_sect_size; 3420 } agsaFlashExtResponse_t; 3421 3422 3423 /** \brief data structure for set fields in MPI table. 3424 * The agsaMPIContext_t data structure is used to set fields in MPI table. 3425 * For details of MPI table, refer to PM8001 Tachyon SPC 8x6G Programmers' 3426 * Manual PMC-2080222 or PM8008/PM8009/PM8018 Tachyon SPCv/SPCve/SPCv+ Programmers Manual 3427 * PMC-2091148/PMC-2102373. 3428 sTSDK section 4.39 3429 */ 3430 3431 typedef struct agsaMPIContext_s 3432 { 3433 bit32 MPITableType; 3434 bit32 offset; 3435 bit32 value; 3436 } agsaMPIContext_t; 3437 3438 #define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1 3439 #define AGSA_MPI_GENERAL_STATUS_TABLE 2 3440 #define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3 3441 #define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4 3442 #define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5 3443 #define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6 3444 #define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7 3445 #define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8 3446 3447 3448 /************************************************************/ 3449 /*This flag and datastructure are specific for fw profiling, Now defined as compiler flag*/ 3450 //#define SPC_ENABLE_PROFILE 3451 3452 #ifdef SPC_ENABLE_PROFILE 3453 typedef struct agsaFwProfile_s 3454 { 3455 bit32 tcid; 3456 bit32 processor; 3457 bit32 cmd; 3458 bit32 len; 3459 bit32 codeStartAdd; 3460 bit32 codeEndAdd; 3461 agsaSgl_t agSgl; 3462 } agsaFwProfile_t; 3463 #endif 3464 /************************************************************/ 3465 /** \brief Callback definition for .ossaDeviceRegistration 3466 * 3467 */ 3468 typedef void (*ossaDeviceRegistrationCB_t)( 3469 agsaRoot_t *agRoot, 3470 agsaContext_t *agContext, 3471 bit32 status, 3472 agsaDevHandle_t *agDevHandle, 3473 bit32 deviceID 3474 ); 3475 3476 /** \brief Callback definition for 3477 * 3478 */ 3479 typedef void (*ossaDeregisterDeviceHandleCB_t)( 3480 agsaRoot_t *agRoot, 3481 agsaContext_t *agContext, 3482 agsaDevHandle_t *agDevHandle, 3483 bit32 status 3484 ); 3485 3486 /** \brief Callback definition for 3487 * 3488 */ 3489 typedef void (*ossaGenericCB_t)(void); 3490 3491 3492 /** \brief Callback definition for abort SMP SSP SATA callback 3493 * 3494 */ 3495 typedef void (*ossaGenericAbortCB_t)( 3496 agsaRoot_t *agRoot, 3497 agsaIORequest_t *agIORequest, 3498 bit32 flag, 3499 bit32 status 3500 ); 3501 3502 3503 typedef void (*ossaLocalPhyControlCB_t)( 3504 agsaRoot_t *agRoot, 3505 agsaContext_t *agContext, 3506 bit32 phyId, 3507 bit32 phyOperation, 3508 bit32 status, 3509 void *parm 3510 ); 3511 3512 3513 /** \brief Callback definition for 3514 * 3515 */ 3516 typedef void (*ossaSATACompletedCB_t)( 3517 agsaRoot_t *agRoot, 3518 agsaIORequest_t *agIORequest, 3519 bit32 agIOStatus, 3520 void *agFirstDword, 3521 bit32 agIOInfoLen, 3522 void *agParam 3523 ); 3524 3525 3526 /** \brief Callback definition for 3527 * 3528 */ 3529 typedef void (*ossaSMPCompletedCB_t)( 3530 agsaRoot_t *agRoot, 3531 agsaIORequest_t *agIORequest, 3532 bit32 agIOStatus, 3533 bit32 agIOInfoLen, 3534 agsaFrameHandle_t agFrameHandle 3535 ); 3536 3537 3538 /** \brief Callback definition for 3539 * 3540 */ 3541 typedef void (*ossaSSPCompletedCB_t)( 3542 agsaRoot_t *agRoot, 3543 agsaIORequest_t *agIORequest, 3544 bit32 agIOStatus, 3545 bit32 agIOInfoLen, 3546 void *agParam, 3547 bit16 sspTag, 3548 bit32 agOtherInfo 3549 ); 3550 3551 /** \brief Callback definition for 3552 * 3553 */ 3554 typedef void (*ossaSetDeviceInfoCB_t) ( 3555 agsaRoot_t *agRoot, 3556 agsaContext_t *agContext, 3557 agsaDevHandle_t *agDevHandle, 3558 bit32 status, 3559 bit32 option, 3560 bit32 param 3561 ); 3562 3563 typedef struct agsaOffloadDifDetails_s 3564 { 3565 bit32 ExpectedCRCUDT01; 3566 bit32 ExpectedUDT2345; 3567 bit32 ActualCRCUDT01; 3568 bit32 ActualUDT2345; 3569 bit32 DIFErr; 3570 bit32 ErrBoffset; 3571 } agsaOffloadDifDetails_t; 3572 3573 typedef struct agsaDifEncPayload_s 3574 { 3575 agsaSgl_t SrcSgl; 3576 bit32 SrcDL; 3577 agsaSgl_t DstSgl; 3578 bit32 DstDL; 3579 agsaDif_t dif; 3580 agsaEncrypt_t encrypt; 3581 } agsaDifEncPayload_t; 3582 3583 typedef void (*ossaVhistCaptureCB_t) ( 3584 agsaRoot_t *agRoot, 3585 agsaContext_t *agContext, 3586 bit32 status, 3587 bit32 len); 3588 3589 typedef void (*ossaDIFEncryptionOffloadStartCB_t) ( 3590 agsaRoot_t *agRoot, 3591 agsaContext_t *agContext, 3592 bit32 status, 3593 agsaOffloadDifDetails_t *agsaOffloadDifDetails 3594 ); 3595 3596 #define SA_RESERVED_REQUEST_COUNT 16 3597 3598 #ifdef SA_FW_TIMER_READS_STATUS 3599 #define SA_FW_TIMER_READS_STATUS_INTERVAL 20 3600 #endif /* SA_FW_TIMER_READS_STATUS */ 3601 3602 #define SIZE_DW 4 /**< Size in bytes */ 3603 #define SIZE_QW 8 /**< Size in bytes */ 3604 3605 #define PCIBAR0 0 /**< PCI Base Address 0 */ 3606 #define PCIBAR1 1 /**< PCI Base Address 1 */ 3607 #define PCIBAR2 2 /**< PCI Base Address 2 */ 3608 #define PCIBAR3 3 /**< PCI Base Address 3 */ 3609 #define PCIBAR4 4 /**< PCI Base Address 4 */ 3610 #define PCIBAR5 5 /**< PCI Base Address 5 */ 3611 3612 /** \brief describe an element of SPC-SPCV converter 3613 * 3614 * This structure is used 3615 * 3616 */ 3617 typedef struct agsaBarOffset_s 3618 { 3619 bit32 Generic; /* */ 3620 bit32 Bar; /* */ 3621 bit32 Offset; /* */ 3622 bit32 Length; /* */ 3623 } agsaBarOffset_t; 3624 3625 typedef union agsabit32bit64_U 3626 { 3627 bit32 S32[2]; 3628 bit64 B64; 3629 } agsabit32bit64; 3630 3631 /* 3632 The agsaIOErrorEventStats_t data structure is used as parameter in ossaGetIOErrorStatsCB(),ossaGetIOEventStatsCB(). 3633 This data structure contains the number of IO error and event. 3634 */ 3635 typedef struct agsaIOErrorEventStats_s 3636 { 3637 bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS; 3638 bit32 agOSSA_IO_ABORTED; 3639 bit32 agOSSA_IO_OVERFLOW; 3640 bit32 agOSSA_IO_UNDERFLOW; 3641 bit32 agOSSA_IO_FAILED; 3642 bit32 agOSSA_IO_ABORT_RESET; 3643 bit32 agOSSA_IO_NOT_VALID; 3644 bit32 agOSSA_IO_NO_DEVICE; 3645 bit32 agOSSA_IO_ILLEGAL_PARAMETER; 3646 bit32 agOSSA_IO_LINK_FAILURE; 3647 bit32 agOSSA_IO_PROG_ERROR; 3648 bit32 agOSSA_IO_DIF_IN_ERROR; 3649 bit32 agOSSA_IO_DIF_OUT_ERROR; 3650 bit32 agOSSA_IO_ERROR_HW_TIMEOUT; 3651 bit32 agOSSA_IO_XFER_ERROR_BREAK; 3652 bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY; 3653 bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED; 3654 bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION; 3655 bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK; 3656 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS; 3657 bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION; 3658 bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED; 3659 bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; 3660 bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION; 3661 bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR; 3662 bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED; 3663 bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT; 3664 bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED; 3665 bit32 agOSSA_IO_XFER_ERROR_RX_FRAME; 3666 bit32 agOSSA_IO_XFER_ERROR_DMA; 3667 bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT; 3668 bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT; 3669 bit32 agOSSA_IO_XFER_ERROR_SATA; 3670 bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST; 3671 bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE; 3672 bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE; 3673 bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT; 3674 bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR; 3675 bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE; 3676 bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN; 3677 bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED; 3678 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT; 3679 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK; 3680 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK; 3681 bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH; 3682 bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN; 3683 bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED; 3684 bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE; 3685 bit32 agOSSA_IO_PORT_IN_RESET; 3686 bit32 agOSSA_IO_DS_NON_OPERATIONAL; 3687 bit32 agOSSA_IO_DS_IN_RECOVERY; 3688 bit32 agOSSA_IO_TM_TAG_NOT_FOUND; 3689 bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR; 3690 bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR; 3691 bit32 agOSSA_IO_DS_IN_ERROR; 3692 bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY; 3693 bit32 agOSSA_IO_ABORT_IN_PROGRESS; 3694 bit32 agOSSA_IO_ABORT_DELAYED; 3695 bit32 agOSSA_IO_INVALID_LENGTH; 3696 bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT; 3697 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED; 3698 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO; 3699 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST; 3700 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE; 3701 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED; 3702 bit32 agOSSA_IO_DS_INVALID; 3703 bit32 agOSSA_IO_XFER_READ_COMPL_ERR; 3704 bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR; 3705 bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR; 3706 bit32 agOSSA_MPI_IO_RQE_BUSY_FULL; 3707 bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE; 3708 bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY; 3709 bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS; 3710 bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH; 3711 bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID; 3712 bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH; 3713 bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR; 3714 bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM; 3715 bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH; 3716 bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH; 3717 bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH; 3718 bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH; 3719 bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME; 3720 bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN; 3721 bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS; 3722 bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED; 3723 bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE; 3724 bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR; 3725 bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED; 3726 bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT; 3727 bit32 agOSSA_IO_UNKNOWN_ERROR; 3728 } agsaIOErrorEventStats_t; 3729 3730 3731 /************************************************************************************ 3732 * * 3733 * Data Structures Defined for LL API ends * 3734 * * 3735 ************************************************************************************/ 3736 #ifdef SALL_API_TEST 3737 typedef struct agsaIOCountInfo_s 3738 { 3739 bit32 numSSPStarted; // saSSPStart() 3740 bit32 numSSPAborted; // saSSPAbort() 3741 bit32 numSSPAbortedCB; // ossaSSPAbortCB() 3742 bit32 numSSPCompleted; // includes success and aborted IOs 3743 bit32 numSMPStarted; // saSMPStart() 3744 bit32 numSMPAborted; // saSMPAbort() 3745 bit32 numSMPAbortedCB; // ossaSMPAbortCB() 3746 bit32 numSMPCompleted; // includes success and aborted IOs 3747 bit32 numSataStarted; // saSATAStart() 3748 bit32 numSataAborted; // saSATAAbort() 3749 bit32 numSataAbortedCB; // ossaSATAAbortCB() 3750 bit32 numSataCompleted; // includes success and aborted IOs 3751 bit32 numEchoSent; // saEchoCommand() 3752 bit32 numEchoCB; // ossaEchoCB() 3753 bit32 numUNKNWRespIOMB; // unknow Response IOMB received 3754 bit32 numOurIntCount; //InterruptHandler() counter 3755 bit32 numSpuriousInt; //spurious interrupts 3756 // bit32 numSpInts[64]; //spuriours interrupts count for each OBQ (PI=CI) 3757 // bit32 numSpInts1[64]; //spuriours interrupts count for each OBQ (PI!=CI) 3758 } agsaIOCountInfo_t; 3759 3760 /* Total IO Counter */ 3761 #define LL_COUNTERS 17 3762 /* Counter Bit Map */ 3763 #define COUNTER_SSP_START 0x000001 3764 #define COUNTER_SSP_ABORT 0x000002 3765 #define COUNTER_SSPABORT_CB 0x000004 3766 #define COUNTER_SSP_COMPLETEED 0x000008 3767 #define COUNTER_SMP_START 0x000010 3768 #define COUNTER_SMP_ABORT 0x000020 3769 #define COUNTER_SMPABORT_CB 0x000040 3770 #define COUNTER_SMP_COMPLETEED 0x000080 3771 #define COUNTER_SATA_START 0x000100 3772 #define COUNTER_SATA_ABORT 0x000200 3773 #define COUNTER_SATAABORT_CB 0x000400 3774 #define COUNTER_SATA_COMPLETEED 0x000800 3775 #define COUNTER_ECHO_SENT 0x001000 3776 #define COUNTER_ECHO_CB 0x002000 3777 #define COUNTER_UNKWN_IOMB 0x004000 3778 #define COUNTER_OUR_INT 0x008000 3779 #define COUNTER_SPUR_INT 0x010000 3780 #define ALL_COUNTERS 0xFFFFFF 3781 3782 typedef union agsaLLCountInfo_s 3783 { 3784 agsaIOCountInfo_t IOCounter; 3785 bit32 arrayIOCounter[LL_COUNTERS]; 3786 } agsaLLCountInfo_t; 3787 3788 #endif /* SALL_API_TEST */ 3789 3790 #define MAX_IO_DEVICE_ENTRIES 4096 /**< Maximum Device Entries */ 3791 3792 3793 #ifdef SA_ENABLE_POISION_TLP 3794 #define SA_PTNFE_POISION_TLP 1 /* Enable if one */ 3795 #else /* SA_ENABLE_POISION_TLP */ 3796 #define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */ 3797 #endif /* SA_ENABLE_POISION_TLP */ 3798 3799 #ifdef SA_DISABLE_MDFD 3800 #define SA_MDFD_MULTI_DATA_FETCH 1 /* Disable if one */ 3801 #else /* SA_DISABLE_MDFD */ 3802 #define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */ 3803 #endif /* SA_DISABLE_MDFD */ 3804 3805 #ifdef SA_ENABLE_ARBTE 3806 #define SA_ARBTE 1 /* Enable if one */ 3807 #else /* SA_ENABLE_ARBTE */ 3808 #define SA_ARBTE 0 /* Disable if zero default setting */ 3809 #endif /* SA_ENABLE_ARBTE */ 3810 3811 #ifdef SA_DISABLE_OB_COAL 3812 #define SA_OUTBOUND_COALESCE 0 /* Disable if zero */ 3813 #else /* SA_DISABLE_OB_COAL */ 3814 #define SA_OUTBOUND_COALESCE 1 /* Enable if one default setting */ 3815 #endif /* SA_DISABLE_OB_COAL */ 3816 3817 3818 /*********************************************************************************** 3819 * * 3820 * The OS Layer Functions Declarations start * 3821 * * 3822 ***********************************************************************************/ 3823 #include "saosapi.h" 3824 /*********************************************************************************** 3825 * * 3826 * The OS Layer Functions Declarations end * 3827 * * 3828 ***********************************************************************************/ 3829 3830 /*********************************************************************************** 3831 * * 3832 * The LL Layer Functions Declarations start * 3833 * * 3834 ***********************************************************************************/ 3835 3836 #ifdef FAST_IO_TEST 3837 /* needs to be allocated by the xPrepare() caller, one struct per IO */ 3838 typedef struct agsaFastCBBuf_s 3839 { 3840 void *cb; 3841 void *cbArg; 3842 void *pSenseData; 3843 bit8 *senseLen; 3844 /* internal */ 3845 void *oneDeviceData; /* tdsaDeviceData_t */ 3846 } agsaFastCBBuf_t; 3847 3848 typedef struct agsaFastCommand_s 3849 { 3850 /* in */ 3851 void *agRoot; 3852 /* modified by TD tiFastPrepare() */ 3853 void *devHandle; /* agsaDevHandle_t* */ 3854 void *agSgl; /* agsaSgl_t* */ 3855 bit32 dataLength; 3856 bit32 extDataLength; 3857 bit8 additionalCdbLen; 3858 bit8 *cdb; 3859 bit8 *lun; 3860 /* modified by TD tiFastPrepare() */ 3861 bit8 taskAttribute; /* TD_xxx */ 3862 bit16 flag; /* TLR_MASK */ 3863 bit32 agRequestType; 3864 bit32 queueNum; 3865 agsaFastCBBuf_t *safb; 3866 } agsaFastCommand_t; 3867 #endif 3868 3869 3870 3871 /* Enable test by setting bits in gFPGA_TEST */ 3872 3873 #define EnableFPGA_TEST_ICCcontrol 0x01 3874 #define EnableFPGA_TEST_ReadDEV 0x02 3875 #define EnableFPGA_TEST_WriteCALAll 0x04 3876 #define EnableFPGA_TEST_ReconfigSASParams 0x08 3877 #define EnableFPGA_TEST_LocalPhyControl 0x10 3878 #define EnableFPGA_TEST_PortControl 0x20 3879 3880 3881 /* 3882 PM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification 3883 SDK2 3884 3.3 Encryption Status Definitions 3885 Encryption engine generated errors. 3886 Table 7 Encryption Engine Generated Errors 3887 Error Definition 3888 */ 3889 3890 /* 3891 PM 1.01 3892 section 4.26.12.6 Encryption Errors 3893 Table 51 lists initialization errors related to encryption functionality. For information on errors reported 3894 for inbound IOMB commands, refer to the corresponding outbound response sections. The error codes 3895 listed in Table 51 are reported in the Scratchpad 3 Register. 3896 */ 3897 #define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Test */ 3898 #define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition is reported based on the bootstrap pin setting. */ 3899 #define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while reading initialization password or Allowable Cipher Modes. */ 3900 #define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initialization password or Allowable Cipher Modes. */ 3901 #define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM doesn't match any valid password value. This could also mean SEEPROM is blank. */ 3902 #define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing initialization password or Allowable Cipher Modes. */ 3903 #define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */ 3904 #define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing to flash memory. */ 3905 #define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing to flash memory. */ 3906 #define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */ 3907 #define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is only detected in Security Mode B. */ 3908 #define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memory. This error is only detected in Security Mode B. */ 3909 #define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */ 3910 #define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */ 3911 3912 /* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */ 3913 /* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */ 3914 /* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */ 3915 /* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */ 3916 /* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */ 3917 /* 0x20:ENC_ERR_FLASH_ACCESS_TMO */ 3918 /* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */ 3919 /* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */ 3920 /* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */ 3921 /* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */ 3922 /* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */ 3923 /* 0x41:ENC_ERR_AES_BIST_FAILURE */ 3924 /* 0x42:ENC_ERR_KWP_BIST_FAILURE */ 3925 3926 /* 3927 This field indicates self test failure in DIF engine bits [27:24]. 3928 */ 3929 3930 #define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */ 3931 3932 #define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */ 3933 #define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */ 3934 #define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */ 3935 #define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */ 3936 3937 #define SA_ROLE_CAPABILITIES_CSP 0x001 3938 #define SA_ROLE_CAPABILITIES_OPR 0x002 3939 #define SA_ROLE_CAPABILITIES_SCO 0x004 3940 #define SA_ROLE_CAPABILITIES_STS 0x008 3941 #define SA_ROLE_CAPABILITIES_TST 0x010 3942 #define SA_ROLE_CAPABILITIES_KEK 0x020 3943 #define SA_ROLE_CAPABILITIES_DEK 0x040 3944 #define SA_ROLE_CAPABILITIES_IOS 0x080 3945 #define SA_ROLE_CAPABILITIES_FWU 0x100 3946 #define SA_ROLE_CAPABILITIES_PRM 0x200 3947 3948 3949 #include "saapi.h" 3950 /*********************************************************************************** 3951 * * 3952 * The LL Layer Functions Declarations end * 3953 * * 3954 ***********************************************************************************/ 3955 3956 #endif /*__SA_H__ */ 3957