1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 /*******************************************************************************/ 24 /*! \file sadefs.h 25 * \brief The file defines the constants used by LL layer 26 */ 27 28 /*******************************************************************************/ 29 30 #ifndef __SADEFS_H__ 31 32 #define __SADEFS_H__ 33 34 #define SA_LL_IBQ_PROTECT 35 36 #define AGSA_MAX_VALID_PORTS AGSA_MAX_VALID_PHYS /**< defines the maximum number of ports */ 37 38 #define NUM_TIMERS 2 /**< defines the maximum number of timers */ 39 #define SA_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 1us */ 40 #define MAX_ACTIVE_IO_REQUESTS 4096 /**< Maximum Active IO Requests */ 41 #define SMP_RESPONSE_FRAMES AGSA_MAX_VALID_PHYS /**< SMP Response Frame Buffer */ 42 #define MAX_NUM_VECTOR 64 /**< Maximum Number of Interrupt Vectors */ 43 #define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error Register Dump Buffer Size */ 44 #define KBYTES 1024 45 46 /* number of IQ/OQ */ 47 #define IQ_NUM_32 32 48 #define OQ_NUM_32 32 49 50 /* default value of Inbound/Outbound element size */ 51 #define INBOUND_DEPTH_SIZE 512 52 #define OUTBOUND_DEPTH_SIZE 512 53 54 /* Priority of Queue */ 55 #define MPI_QUEUE_NORMAL 0 56 #define MPI_QUEUE_PRIORITY 1 57 58 /* size of IOMB - multiple with 32 bytes */ 59 #define IOMB_SIZE64 64 60 #define IOMB_SIZE96 96 61 #define IOMB_SIZE128 128 62 #define IOMB_SIZE256 256 63 64 /* DIR bit of IOMB for SSP read/write command */ 65 #define DIR_NODATA 0x000 66 #define DIR_READ 0x100 67 #define DIR_WRITE 0x200 68 69 /* TLR bits mask */ 70 #define TLR_MASK 0x00000003 71 /* port and phy Id bits Mask */ 72 73 74 #define PORTID_MASK 0x0000000F 75 #define PORTID_V_MASK 0x000000FF 76 #define PHYID_MASK 0x0000000F 77 #define PHYID_V_MASK 0x000000FF 78 #define PORT_STATE_MASK 0x0000000F 79 #define PHY_IN_PORT_MASK 0x000000F0 80 81 #define SM_PHYID_MASK (smIS_SPC(agRoot) ? PHYID_MASK : PHYID_V_MASK ) 82 #define SM_PORTID_MASK (smIS_SPC(agRoot) ? PORTID_MASK : PORTID_V_MASK ) 83 84 /* the index for memory requirement, must be continious */ 85 #define LLROOT_MEM_INDEX 0 /**< the index of root memory */ 86 #define DEVICELINK_MEM_INDEX (LLROOT_MEM_INDEX + 1) /**< the index of device descriptors memory */ 87 #define IOREQLINK_MEM_INDEX (DEVICELINK_MEM_INDEX+1) /**< the index of IO requests memory */ 88 89 #ifdef SA_ENABLE_HDA_FUNCTIONS 90 #define HDA_DMA_BUFFER (IOREQLINK_MEM_INDEX+1) /** HDA Buffer */ 91 #else /* SA_ENABLE_HDA_FUNCTIONS */ 92 #define HDA_DMA_BUFFER (IOREQLINK_MEM_INDEX) /** HDA Buffer */ 93 #endif /* SA_ENABLE_HDA_FUNCTIONS */ 94 95 #ifdef SA_ENABLE_TRACE_FUNCTIONS 96 #define LL_FUNCTION_TRACE (HDA_DMA_BUFFER+1) /**TraceLog */ 97 #else /* SA_ENABLE_TRACE_FUNCTIONS */ 98 #define LL_FUNCTION_TRACE HDA_DMA_BUFFER /**TraceLog */ 99 #endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 100 101 #define TIMERLINK_MEM_INDEX (LL_FUNCTION_TRACE+1) /**< the index of timers memory */ 102 103 #ifdef FAST_IO_TEST 104 #define LL_FAST_IO (TIMERLINK_MEM_INDEX+1) 105 #define MPI_IBQ_OBQ_INDEX (LL_FAST_IO + 1) 106 107 #else /* FAST_IO_TEST */ 108 109 #define LL_FAST_IO TIMERLINK_MEM_INDEX 110 #define MPI_IBQ_OBQ_INDEX (LL_FAST_IO + 1) 111 #endif /* FAST_IO_TEST */ 112 113 #define MPI_MEM_INDEX (MPI_IBQ_OBQ_INDEX - LLROOT_MEM_INDEX) 114 115 #define MPI_EVENTLOG_INDEX 0 116 #define MPI_IOP_EVENTLOG_INDEX 1 117 #define MPI_CI_INDEX 2 118 /* The following is a reference index */ 119 #define MPI_PI_INDEX (MPI_CI_INDEX + 1) 120 #define MPI_IBQ_INDEX (MPI_PI_INDEX + 1) 121 #define MPI_OBQ_INDEX (MPI_IBQ_INDEX + MPI_MAX_INBOUND_QUEUES) 122 123 #define TOTAL_MPI_MEM_CHUNKS (MPI_MAX_INBOUND_QUEUES * 2) + MPI_IBQ_INDEX 124 125 126 #define LL_DEVICE_LOCK 0 127 #define LL_PORT_LOCK (LL_DEVICE_LOCK+1) 128 #define LL_TIMER_LOCK (LL_PORT_LOCK+1) 129 #define LL_IOREQ_LOCKEQ_LOCK (LL_TIMER_LOCK+1) 130 131 #ifdef FAST_IO_TEST 132 #define LL_FAST_IO_LOCK (LL_IOREQ_LOCKEQ_LOCK+1) 133 #else /* FAST_IO_TEST */ 134 #define LL_FAST_IO_LOCK (LL_IOREQ_LOCKEQ_LOCK) 135 #endif /* FAST_IO_TEST */ 136 137 #ifdef SA_ENABLE_TRACE_FUNCTIONS 138 #define LL_TRACE_LOCK (LL_FAST_IO_LOCK+1) 139 #else /* SA_ENABLE_TRACE_FUNCTIONS */ 140 #define LL_TRACE_LOCK (LL_FAST_IO_LOCK) 141 #endif /* SA_ENABLE_TRACE_FUNCTIONS */ 142 143 #ifdef MPI_DEBUG_TRACE_ENABLE 144 #define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK+1) 145 #else /* MPI_DEBUG_TRACE_ENABLE */ 146 #define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK) 147 #endif /* MPI_DEBUG_TRACE_ENABLE */ 148 149 #define LL_IOREQ_OBQ_LOCK (LL_IOMB_TRACE_LOCK+1) 150 151 #define LL_IOREQ_IBQ_LOCK (LL_IOREQ_OBQ_LOCK +1) 152 #define LL_IOREQ_IBQ_LOCK_PARM (LL_IOREQ_OBQ_LOCK + queueConfig->numOutboundQueues +1) 153 #define LL_IOREQ_IBQ0_LOCK (LL_IOREQ_OBQ_LOCK + saRoot->QueueConfig.numOutboundQueues +1) 154 155 156 157 /* define phy states */ 158 #define PHY_STOPPED 0x00000000 /**< flag indicates phy stopped */ 159 #define PHY_UP 0x00000001 /**< flag indicates phy up */ 160 #define PHY_DOWN 0x00000002 /**< flag indicates phy down */ 161 162 /* define port states */ 163 #define PORT_NORMAL 0x0000 164 #define PORT_INVALIDATING 0x0002 165 166 /* define chip status */ 167 #define CHIP_NORMAL 0x0000 168 #define CHIP_SHUTDOWN 0x0001 169 #define CHIP_RESETTING 0x0002 170 #define CHIP_RESET_FW 0x0004 171 #define CHIP_FATAL_ERROR 0x0008 172 173 /* define device types */ 174 #define SAS_SATA_UNKNOWN_DEVICE 0xFF /**< SAS SATA unknown device type */ 175 176 #define STP_DEVICE 0x00 /**< SATA device behind an expander */ 177 #define SSP_SMP_DEVICE 0x01 /**< SSP or SMP device type */ 178 #define DIRECT_SATA_DEVICE 0x02 /**< SATA direct device type */ 179 180 /* SATA */ 181 #define SATA_FIS_MASK 0x00000001 182 #define MAX_SATARESP_SUPPORT_BYTES 44 183 184 #define MARK_OFF 0xFFFFFFFF 185 #define PORT_MARK_OFF 0xFFFFFFFF 186 #define NO_FATAL_ERROR_VECTOR 0xFFFFFFFF 187 188 #define SATA_PROTOCOL_RSRT_ASSERT 0x01 189 #define SATA_PROTOCOL_RSRT_DEASSERT 0x02 190 #define SATA_NON_DATA_PROTOCOL 0x0d 191 #define SATA_PIO_READ_PROTOCOL 0x0e 192 #define SATA_DMA_READ_PROTOCOL 0x0f 193 #define SATA_FPDMA_READ_PROTOCOL 0x10 194 #define SATA_PIO_WRITE_PROTOCOL 0x11 195 #define SATA_DMA_WRITE_PROTOCOL 0x12 196 #define SATA_FPDMA_WRITE_PROTOCOL 0x13 197 #define SATA_DEVICE_RESET_PROTOCOL 0x14 198 199 /* Definition for bit shift */ 200 #define SHIFT0 0 201 #define SHIFT1 1 202 #define SHIFT2 2 203 #define SHIFT3 3 204 #define SHIFT4 4 205 #define SHIFT5 5 206 #define SHIFT6 6 207 #define SHIFT7 7 208 #define SHIFT8 8 209 #define SHIFT9 9 210 #define SHIFT10 10 211 #define SHIFT11 11 212 #define SHIFT12 12 213 #define SHIFT13 13 214 #define SHIFT14 14 215 #define SHIFT15 15 216 #define SHIFT16 16 217 #define SHIFT17 17 218 #define SHIFT18 18 219 #define SHIFT19 19 220 #define SHIFT20 20 221 #define SHIFT21 21 222 #define SHIFT22 22 223 #define SHIFT23 23 224 #define SHIFT24 24 225 #define SHIFT25 25 226 #define SHIFT26 26 227 #define SHIFT27 27 228 #define SHIFT28 28 229 #define SHIFT29 29 230 #define SHIFT30 30 231 #define SHIFT31 31 232 233 /* These flags used for saSSPAbort(), saSATAAbort() */ 234 #define ABORT_MASK 0x3 235 #define ABORT_SINGLE 0x0 236 #define ABORT_SCOPE 0x3 /* bits 0-1*/ 237 #define ABORT_ALL 0x1 238 #define ABORT_TSDK_QUARANTINE 0x4 239 #define ABORT_QUARANTINE_SPC 0x4 240 #define ABORT_QUARANTINE_SPCV 0x8 241 242 /* These flags used for saGetRegDump() */ 243 #define REG_DUMP_NUM0 0x0 244 #define REG_DUMP_NUM1 0x1 245 #define REG_DUMP_NONFLASH 0x0 246 #define REG_DUMP_FLASH 0x1 247 248 /* MSIX Interupts */ 249 #define MSIX_TABLE_OFFSET 0x2000 250 #define MSIX_TABLE_ELEMENT_SIZE 0x10 251 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC 252 #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET+MSIX_INTERRUPT_CONTROL_OFFSET) 253 #define MSIX_INTERRUPT_DISABLE 0x1 254 #define MSIX_INTERRUPT_ENABLE 0x0 255 256 #define MAX_QUEUE_EACH_MEM 8 257 258 #define NUM_MEM_CHUNKS(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q/rem+1) : (bit32)(Q/rem)) 259 #define NUM_QUEUES_IN_MEM(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q%rem) : (bit32)(MAX_QUEUE_EACH_MEM)) 260 261 #define MAX_DEV_BITS 0xFFFF0000 262 #define PHY_COUNT_BITS 0x01f80000 263 #define Q_SUPPORT_BITS 0x0007ffff 264 #define SAS_SPEC_BITS 0xfe000000 265 #define HP_SUPPORT_BIT 0x00010000 266 #define INT_COL_BIT 0x00040000 267 #define INT_DELAY_BITS 0xFFFF 268 #define INT_THR_BITS 0xFF 269 #define INT_VEC_BITS 0xFF 270 271 #define AUTO_HARD_RESET_DEREG_FLAG 0x00000001 272 #define AUTO_FW_CLEANUP_DEREG_FLAG 0x00000002 273 274 #define BYTE_MASK 0xff 275 276 #define INT_OPTION 0x7FFF 277 #define SMP_TO_DEFAULT 100 278 #define ITL_TO_DEFAULT 0xFFFF 279 280 281 /* 282 agsaHwConfig_s hwOption 283 */ 284 #define HW_CFG_PICI_EFFECTIVE_ADDRESS 0x1 285 286 /* SPC or SPCv ven dev Id */ 287 288 #define SUBID_SPC 0x00000000 289 #define SUBID_SPCV 0x56781234 290 291 #define VEN_DEV_SPC 0x80010000 292 #define VEN_DEV_HIL 0x80810000 293 294 #define VEN_DEV_SPCV 0x80080000 295 #define VEN_DEV_SPCVE 0x80090000 296 #define VEN_DEV_SPCVP 0x80180000 297 #define VEN_DEV_SPCVEP 0x80190000 298 299 #define VEN_DEV_SPC12V 0x80700000 300 #define VEN_DEV_SPC12VE 0x80710000 301 #define VEN_DEV_SPC12VP 0x80720000 302 #define VEN_DEV_SPC12VEP 0x80730000 303 #define VEN_DEV_9015 0x90150000 304 #define VEN_DEV_9060 0x90600000 305 306 #define VEN_DEV_ADAPVEP 0x80890000 307 #define VEN_DEV_ADAPVP 0x80880000 308 309 310 #define VEN_DEV_SFC 0x80250000 311 312 /*DelRay PCIid */ 313 #define VEN_DEV_SPC12ADP 0x80740000 /* 8 ports */ 314 #define VEN_DEV_SPC12ADPE 0x80750000 /* 8 ports encrypt */ 315 #define VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */ 316 #define VEN_DEV_SPC12ADPEP 0x80770000 /* 16 ports encrypt */ 317 #define VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */ 318 319 #endif /*__SADEFS_H__ */ 320