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Searched refs:SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_car.h222 #define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6) macro
H A Dtegra124_clk_pll.c651 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; in plle_enable()
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_car.h307 #define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6) macro
H A Dtegra210_clk_pll.c850 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; in plle_enable()