Home
last modified time | relevance | path

Searched refs:SALU (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp56 if (MIFlags & SIInstrFlags::SALU) { in instructionWaitsForSGPRWrites()
66 enum DelayType { VALU, TRANS, SALU, OTHER }; enumerator
74 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
75 return SALU; in getDelayType()
132 case SALU: in DelayInfo()
H A DAMDGPUWaitSGPRHazards.cpp117 static constexpr unsigned SALU = (1 << 0); member
251 State.VCCHazard &= ~HazardState::SALU; in runOnMachineBasicBlock()
333 if (State.VCCHazard & HazardState::SALU) in runOnMachineBasicBlock()
341 State.VCCHazard = IsSALU ? HazardState::SALU : HazardState::VALU; in runOnMachineBasicBlock()
368 if (State.SALUHazards.any() || (State.VCCHazard & HazardState::SALU)) in runOnMachineBasicBlock()
397 State.VCCHazard &= ~HazardState::SALU; in runOnMachineBasicBlock()
H A DSIInstrFormats.td17 field bit SALU = 0;
20 // SALU instruction formats.
163 let TSFlags{0} = SALU;
275 let SALU = 1;
H A DAMDGPUIGroupLP.cpp69 SALU = 1u << 2, enumerator
78 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
2403 else if (((SGMask & SchedGroupMask::SALU) != SchedGroupMask::NONE) && in canAddMI()
2620 InvertedMask &= ~SchedGroupMask::VALU & ~SchedGroupMask::SALU & in invertSchedBarrierMask()
2624 (InvertedMask & SchedGroupMask::SALU) == SchedGroupMask::NONE || in invertSchedBarrierMask()
H A DSIInstrInfo.h428 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
432 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
887 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
H A DSOPInstructions.td37 let SALU = 1;
51 let SALU = 1;
524 let SALU = 1;
541 let SALU = 1;
945 let SALU = 1;
957 let SALU = 1;
1218 let SALU = 1;
1229 let SALU = 1;
1404 let SALU = 1;
1422 let SALU = 1;
H A DSIDefines.h56 SALU = 1 << 0, enumerator
H A DSISchedule.td76 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
H A DSIInstructions.td383 } // End let usesCustomInserter = 1, SALU = 1
539 // This uses SCC from a previous SALU operation, i.e. the update of
588 let SALU = 1;
595 let SALU = 1;
889 let SALU = 1;
978 let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
H A DAMDGPU.td1082 "Has SALU floating point instructions"
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td318 // MASK = 0x0000 0004: SALU instructions may be scheduled across SCHED_BARRIER.