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Searched refs:SALU (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp60 enum DelayType { VALU, TRANS, SALU, OTHER }; enumerator
68 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
69 return SALU; in getDelayType()
126 case SALU: in DelayInfo()
H A DSIInstrFormats.td17 field bit SALU = 0;
20 // SALU instruction formats.
159 let TSFlags{0} = SALU;
270 let SALU = 1;
H A DSIInstrInfo.h409 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
413 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
850 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
H A DSOPInstructions.td37 let SALU = 1;
51 let SALU = 1;
548 let SALU = 1;
565 let SALU = 1;
966 let SALU = 1;
978 let SALU = 1;
1238 let SALU = 1;
1249 let SALU = 1;
1423 let SALU = 1;
1441 let SALU = 1;
H A DAMDGPUIGroupLP.cpp70 SALU = 1u << 2, enumerator
79 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
2403 else if (((SGMask & SchedGroupMask::SALU) != SchedGroupMask::NONE) && in canAddMI()
2624 InvertedMask &= ~SchedGroupMask::VALU & ~SchedGroupMask::SALU & in invertSchedBarrierMask()
2628 (InvertedMask & SchedGroupMask::SALU) == SchedGroupMask::NONE || in invertSchedBarrierMask()
H A DSIDefines.h55 SALU = 1 << 0, enumerator
H A DSISchedule.td75 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
H A DSIInstructions.td332 } // End let usesCustomInserter = 1, SALU = 1
497 // This uses SCC from a previous SALU operation, i.e. the update of
546 let SALU = 1;
553 let SALU = 1;
812 let SALU = 1;
901 let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
H A DAMDGPU.td929 "Has SALU floating point instructions"
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td291 // MASK = 0x0000 0004: SALU instructions may be scheduled across SCHED_BARRIER.