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Searched refs:SADDSAT (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3747 { ISD::SADDSAT, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3748 { ISD::SADDSAT, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3815 { ISD::SADDSAT, MVT::v2i64, { 3, 3, 8, 9 } }, in getIntrinsicInstrCost()
3816 { ISD::SADDSAT, MVT::v4i64, { 2, 2, 6, 7 } }, in getIntrinsicInstrCost()
3817 { ISD::SADDSAT, MVT::v8i64, { 3, 3, 6, 7 } }, in getIntrinsicInstrCost()
3818 { ISD::SADDSAT, MVT::v4i32, { 2, 2, 6, 7 } }, in getIntrinsicInstrCost()
3819 { ISD::SADDSAT, MVT::v8i32, { 2, 2, 6, 7 } }, in getIntrinsicInstrCost()
3820 { ISD::SADDSAT, MVT::v16i32, { 3, 3, 6, 7 } }, in getIntrinsicInstrCost()
3821 { ISD::SADDSAT, MVT::v32i16, { 2, 2, 2, 2 } }, in getIntrinsicInstrCost()
3822 { ISD::SADDSAT, MVT::v64i8, { 2, 2, 2, 2 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1155 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal); in X86TargetLowering()
1159 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal); in X86TargetLowering()
1378 setOperationAction(ISD::SADDSAT, MVT::v2i64, Custom); in X86TargetLowering()
1610 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1614 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1995 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
29205 if ((Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) && in LowerADDSAT_SUBSAT()
29211 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
33705 case ISD::SADDSAT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h360 SADDSAT, enumerator
H A DBasicTTIImpl.h2510 ISD = ISD::SADDSAT; in getTypeBasedIntrinsicInstrCost()
H A DTargetLowering.h2986 case ISD::SADDSAT: in isCommutativeBinOp()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp374 case ISD::SADDSAT: return "saddsat"; in getOperationName()
H A DLegalizeVectorOps.cpp466 case ISD::SADDSAT: in LegalizeOp()
1174 case ISD::SADDSAT: in Expand()
H A DLegalizeIntegerTypes.cpp248 case ISD::SADDSAT: in PromoteIntegerResult()
1133 case ISD::SADDSAT: in PromoteIntRes_ADDSUBSHLSAT()
1157 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
3084 case ISD::SADDSAT: in ExpandIntegerResult()
H A DSelectionDAG.cpp5541 case ISD::SADDSAT: in canCreateUndefOrPoison()
6684 case ISD::SADDSAT: return C1.sadd_sat(C2); in FoldValue()
7522 case ISD::SADDSAT: in getNode()
7531 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
7902 case ISD::SADDSAT: in getNode()
H A DTargetLowering.cpp10842 case ISD::SADDSAT: in expandAddSubSat()
10893 if (Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) { in expandAddSubSat()
10908 bool RHSIsNonNegative = Opcode == ISD::SADDSAT ? KnownRHS.isNonNegative() in expandAddSubSat()
10916 bool RHSIsNegative = Opcode == ISD::SADDSAT ? KnownRHS.isNegative() in expandAddSubSat()
11434 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT; in expandSADDSUBO()
H A DLegalizeVectorTypes.cpp170 case ISD::SADDSAT: in ScalarizeVectorResult()
1333 case ISD::SADDSAT: case ISD::VP_SADDSAT: in SplitVectorResult()
4764 case ISD::SADDSAT: case ISD::VP_SADDSAT: in WidenVectorResult()
H A DLegalizeDAG.cpp1180 case ISD::SADDSAT: in LegalizeOp()
4029 case ISD::SADDSAT: in ExpandNode()
H A DSelectionDAGBuilder.cpp7232 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
H A DDAGCombiner.cpp1899 case ISD::SADDSAT: in visit()
3182 bool IsSigned = Opcode == ISD::SADDSAT; in visitADDSAT()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def282 VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp801 ISD::SADDSAT, ISD::UADDSAT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1765 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in HexagonTargetLowering()
1766 setOperationAction(ISD::SADDSAT, MVT::i64, Legal); in HexagonTargetLowering()
H A DHexagonISelLoweringHVX.cpp210 setOperationAction(ISD::SADDSAT, T, Legal); in initializeHVXLowering()
303 setOperationAction(ISD::SADDSAT, T, Legal); in initializeHVXLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp229 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
287 setOperationAction(ISD::SADDSAT, VT, Legal); in addMVEVectorTypes()
1152 setOperationAction(ISD::SADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1154 setOperationAction(ISD::SADDSAT, MVT::i16, Custom); in ARMTargetLowering()
1162 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in ARMTargetLowering()
5159 case ISD::SADDSAT: in LowerADDSUBSAT()
5175 case ISD::SADDSAT: in LowerADDSUBSAT()
7930 case ISD::SADDSAT: in IsQRMVEInstruction()
10710 case ISD::SADDSAT: in LowerOperation()
10817 case ISD::SADDSAT: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp339 {ISD::SADDSAT, ISD::SSUBSAT, ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, in RISCVTargetLowering()
445 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in RISCVTargetLowering()
898 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
1368 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
6981 OP_CASE(SADDSAT) in getRISCVVLOp()
7028 VP_CASE(SADDSAT) // VP_SADDSAT in getRISCVVLOp()
8154 case ISD::SADDSAT: in LowerOperation()
14440 case ISD::SADDSAT: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td468 def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp216 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in WebAssemblyTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp531 setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32}, in SITargetLowering()
802 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
822 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
6205 case ISD::SADDSAT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp645 ISD::SADDSAT, ISD::SDIV, ISD::SDIVREM, ISD::SELECT_CC, in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1327 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
1570 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
6011 return DAG.getNode(ISD::SADDSAT, DL, Op.getValueType(), Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
22287 return convertMergedOpToPredOp(N, ISD::SADDSAT, DAG, true); in performIntrinsicCombine()
22297 return DAG.getNode(ISD::SADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()

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