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Searched refs:SADDSAT (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h347 SADDSAT, enumerator
H A DTargetLowering.h2902 case ISD::SADDSAT: in isCommutativeBinOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3593 { ISD::SADDSAT, MVT::v32i16, { 1 } }, in getIntrinsicInstrCost()
3594 { ISD::SADDSAT, MVT::v64i8, { 1 } }, in getIntrinsicInstrCost()
3689 { ISD::SADDSAT, MVT::v32i16, { 2 } }, in getIntrinsicInstrCost()
3690 { ISD::SADDSAT, MVT::v64i8, { 2 } }, in getIntrinsicInstrCost()
3800 { ISD::SADDSAT, MVT::v16i16, { 1 } }, in getIntrinsicInstrCost()
3801 { ISD::SADDSAT, MVT::v32i8, { 1 } }, in getIntrinsicInstrCost()
3886 { ISD::SADDSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
3887 { ISD::SADDSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
4038 { ISD::SADDSAT, MVT::v8i16, { 1 } }, in getIntrinsicInstrCost()
4039 { ISD::SADDSAT, MVT::v16i8, { 1 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1134 setOperationAction(ISD::SADDSAT, MVT::v16i8, Legal); in X86TargetLowering()
1138 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal); in X86TargetLowering()
1357 setOperationAction(ISD::SADDSAT, MVT::v2i64, Custom); in X86TargetLowering()
1586 setOperationAction(ISD::SADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1590 setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1963 setOperationAction(ISD::SADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
28183 if ((Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) && in LowerADDSAT_SUBSAT()
28189 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
32480 case ISD::SADDSAT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp357 case ISD::SADDSAT: return "saddsat"; in getOperationName()
H A DLegalizeVectorOps.cpp449 case ISD::SADDSAT: in LegalizeOp()
1043 case ISD::SADDSAT: in Expand()
H A DLegalizeIntegerTypes.cpp228 case ISD::SADDSAT: in PromoteIntegerResult()
1084 case ISD::SADDSAT: in PromoteIntRes_ADDSUBSHLSAT()
1111 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
2901 case ISD::SADDSAT: in ExpandIntegerResult()
H A DSelectionDAG.cpp5257 case ISD::SADDSAT: in canCreateUndefOrPoison()
6270 case ISD::SADDSAT: return C1.sadd_sat(C2); in FoldValue()
6977 case ISD::SADDSAT: in getNode()
6986 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
7373 case ISD::SADDSAT: in getNode()
H A DTargetLowering.cpp10350 case ISD::SADDSAT: in expandAddSubSat()
10401 if (Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) { in expandAddSubSat()
10416 bool RHSIsNonNegative = Opcode == ISD::SADDSAT ? KnownRHS.isNonNegative() in expandAddSubSat()
10424 bool RHSIsNegative = Opcode == ISD::SADDSAT ? KnownRHS.isNegative() in expandAddSubSat()
10932 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT; in expandSADDSUBO()
H A DLegalizeVectorTypes.cpp159 case ISD::SADDSAT: in ScalarizeVectorResult()
1274 case ISD::SADDSAT: case ISD::VP_SADDSAT: in SplitVectorResult()
4396 case ISD::SADDSAT: case ISD::VP_SADDSAT: in WidenVectorResult()
H A DLegalizeDAG.cpp1150 case ISD::SADDSAT: in LegalizeOp()
3890 case ISD::SADDSAT: in ExpandNode()
H A DSelectionDAGBuilder.cpp7180 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
H A DDAGCombiner.cpp1841 case ISD::SADDSAT: in visit()
3022 bool IsSigned = Opcode == ISD::SADDSAT; in visitADDSAT()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def309 VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp720 ISD::SADDSAT, ISD::UADDSAT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp224 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
282 setOperationAction(ISD::SADDSAT, VT, Legal); in addMVEVectorTypes()
1150 setOperationAction(ISD::SADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1152 setOperationAction(ISD::SADDSAT, MVT::i16, Custom); in ARMTargetLowering()
1160 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in ARMTargetLowering()
5096 case ISD::SADDSAT: in LowerADDSUBSAT()
5112 case ISD::SADDSAT: in LowerADDSUBSAT()
7880 case ISD::SADDSAT: in IsQRMVEInstruction()
10649 case ISD::SADDSAT: in LowerOperation()
10754 case ISD::SADDSAT: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp289 setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom); in RISCVTargetLowering()
293 setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom); in RISCVTargetLowering()
850 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
1249 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
5691 bool IsAdd = Op.getOpcode() == ISD::SADDSAT; in lowerSADDSAT_SSUBSAT()
5975 OP_CASE(SADDSAT) in getRISCVVLOp()
6022 VP_CASE(SADDSAT) // VP_SADDSAT in getRISCVVLOp()
7041 case ISD::SADDSAT: in LowerOperation()
12558 case ISD::SADDSAT: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp198 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td452 def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp516 setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32}, in SITargetLowering()
776 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
795 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
5860 case ISD::SADDSAT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp534 ISD::SADDSAT, ISD::SDIV, ISD::SDIVREM, ISD::SELECT_CC, in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1275 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
1478 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
21426 return convertMergedOpToPredOp(N, ISD::SADDSAT, DAG, true); in performIntrinsicCombine()
21436 return DAG.getNode(ISD::SADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp777 setOperationAction(ISD::SADDSAT, VT, Legal); in PPCTargetLowering()