| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 330 SADDO, enumerator
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| H A D | SelectionDAGNodes.h | 3263 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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| H A D | TargetLowering.h | 2898 case ISD::SADDO: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 101 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
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| H A D | SystemZISelDAGToDAG.cpp | 1410 case SystemZISD::SADDO: in tryFoldLoadStoreIntoMemOperand()
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| H A D | SystemZOperators.td | 291 def z_saddo : SDNode<"SystemZISD::SADDO", SDT_ZBinaryWithFlags>;
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| H A D | SystemZISelLowering.cpp | 189 setOperationAction(ISD::SADDO, VT, Custom); in SystemZTargetLowering()
4310 case ISD::SADDO: in lowerXALUO()
4311 BaseOp = SystemZISD::SADDO; in lowerXALUO()
6162 case ISD::SADDO: in LowerOperation()
6398 OPCODE(SADDO); in getTargetNodeName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 116 setOperationAction(ISD::SADDO, VT, Custom); in M68kTargetLowering()
1382 case ISD::SADDO: in LowerOperation()
1539 case ISD::SADDO: in isOverflowArithmetic()
1578 case ISD::SADDO: in lowerOverflowArithmetic()
2464 (Cond.getOperand(0).getOpcode() == ISD::SADDO || in LowerBRCOND()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 343 case ISD::SADDO: return "saddo"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 441 case ISD::SADDO: in LegalizeOp()
1032 case ISD::SADDO: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 213 case ISD::SADDO: in PromoteIntegerResult()
1290 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_SADDSUBO()
2894 case ISD::SADDO: in ExpandIntegerResult()
4481 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && in ExpandIntRes_SADDSUBO()
4489 bool IsAdd = Node->getOpcode() == ISD::SADDO; in ExpandIntRes_SADDSUBO()
4509 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? in ExpandIntRes_SADDSUBO()
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| H A D | SelectionDAG.cpp | 3921 case ISD::SADDO: in computeKnownBits()
4708 case ISD::SADDO: in ComputeNumSignBits()
10174 case ISD::SADDO: in getNode()
10201 if (Opcode == ISD::UADDO || Opcode == ISD::SADDO) in getNode()
12480 assert((Opcode == ISD::UADDO || Opcode == ISD::SADDO || in UnrollVectorOverflowOp()
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| H A D | LegalizeVectorTypes.cpp | 210 case ISD::SADDO: in ScalarizeVectorResult()
1309 case ISD::SADDO: in SplitVectorResult()
4466 case ISD::SADDO: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1846 case ISD::SADDO: in visit()
3300 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO()
3695 TLI.isOperationLegalOrCustom(ISD::SADDO, N->getValueType(0))) in visitSADDO_CARRY()
3696 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1); in visitSADDO_CARRY()
4223 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, in visitSUBO()
5490 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL, in visitMULO()
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| H A D | TargetLowering.cpp | 10351 OverflowOp = ISD::SADDO; in expandAddSubSat()
10922 bool IsAdd = Node->getOpcode() == ISD::SADDO; in expandSADDSUBO()
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| H A D | LegalizeDAG.cpp | 3973 case ISD::SADDO: in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 7493 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 4114 { ISD::SADDO, MVT::i64, { 1 } }, in getIntrinsicInstrCost()
4166 { ISD::SADDO, MVT::i32, { 1 } }, in getIntrinsicInstrCost()
4167 { ISD::SADDO, MVT::i16, { 1 } }, in getIntrinsicInstrCost()
4168 { ISD::SADDO, MVT::i8, { 1 } }, in getIntrinsicInstrCost()
4278 ISD = ISD::SADDO; in getIntrinsicInstrCost()
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| H A D | X86ISelLowering.cpp | 2433 setOperationAction(ISD::SADDO, VT, Custom); in X86TargetLowering()
23965 case ISD::SADDO: in getX86XALUOOp()
24264 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT()
28189 DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL, in LowerADDSAT_SUBSAT()
32465 case ISD::SADDO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 732 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1570 setOperationAction(ISD::SADDO, VT, Expand); in HexagonTargetLowering()
1647 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1142 setOperationAction(ISD::SADDO, MVT::i32, Custom); in ARMTargetLowering()
4943 case ISD::SADDO: in getARMXALUOOp()
5141 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerSELECT()
5723 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBRCOND()
5774 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || in LowerBR_CC()
10643 case ISD::SADDO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 297 setOperationAction(ISD::SADDO, MVT::i32, Custom); in RISCVTargetLowering()
5721 // Custom lower i32 SADDO/SSUBO with RV64LegalI32 so we take advantage of addw. in lowerSADDO_SSUBO()
5728 bool IsAdd = Op.getOpcode() == ISD::SADDO; in lowerSADDO_SSUBO()
6272 case ISD::SADDO: in LowerOperation()
12464 case ISD::SADDO: { in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 533 ISD::ROTL, ISD::ROTR, ISD::SADDO, ISD::SADDO_CARRY, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 697 setOperationAction(ISD::SADDO, MVT::i32, Custom); in AArch64TargetLowering()
698 setOperationAction(ISD::SADDO, MVT::i64, Custom); in AArch64TargetLowering()
3986 case ISD::SADDO: in getAArch64XALUOOp()
6804 case ISD::SADDO: in LowerOperation()
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