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Searched refs:Rs (Results 1 – 25 of 64) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
128 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>;
129 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>;
254 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
255 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
256 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
257 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
258 def ToAext64: OutPatFrag<(ops node:$Rs),
259 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
261 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
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H A DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
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H A DHexagonRegisterInfo.td90 // Rs - system registers
91 class Rs<bits<7> num, string n,
289 def SGP0 : Rs<0, "sgp0", ["s0"]>, DwarfRegNum<[144]>;
290 def SGP1 : Rs<1, "sgp1", ["s1"]>, DwarfRegNum<[145]>;
291 def STID : Rs<2, "stid", ["s2"]>, DwarfRegNum<[146]>;
292 def ELR : Rs<3, "elr", ["s3"]>, DwarfRegNum<[147]>;
293 def BADVA0 : Rs<4, "badva0", ["s4"]>, DwarfRegNum<[148]>;
294 def BADVA1 : Rs<5, "badva1", ["s5"]>, DwarfRegNum<[149]>;
295 def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>;
296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>;
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H A DHexagonConstExtenders.cpp284 Register Rs; member
289 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {} in ExtExpr()
292 return Rs.Reg == 0; in trivial()
295 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg; in operator ==()
301 return std::tie(Rs, S, Neg) < std::tie(Ex.Rs, Ex.S, Ex.Neg); in operator <()
433 : Rs(R), HRI(I) {} in PrintRegister()
434 HCE::Register Rs; member
440 if (P.Rs.Reg != 0) in operator <<()
441 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
457 if (P.Ex.Rs.Reg != 0) in operator <<()
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H A DHexagonPatternsHVX.td300 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
301 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
302 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
303 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
304 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
305 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
348 def: Pat<(VecI8 (splat_vector I32:$Rs)), (PS_vsplatrb $Rs)>;
349 def: Pat<(VecI16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>;
350 def: Pat<(VecI32 (splat_vector I32:$Rs)), (PS_vsplatrw $Rs)>;
351 def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (PS_vsplatrb $Rs))>;
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H A DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
302 // Rd=[cround|round](Rs,Rt)[:sat]
303 // Rd=[cround|round](Rs,#u5)[:sat]
328 // Rdd=vmpyb[s]u(Rs,Rt)
332 // Rxx+=vmpyb[s]u(Rs,Rt)
H A DHexagonSplitDouble.cpp97 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
141 const USet &Rs = I.second; in isInduction() local
142 if (Rs.find(Reg) != Rs.end()) in isInduction()
367 Register Rs = MI->getOperand(1).getReg(); in profit() local
369 return profit(Rs) + profit(Rt); in profit()
469 USet &Rs) { in collectIndRegsForLoop() argument
553 Rs.insert(DP.begin(), End); in collectIndRegsForLoop()
554 Rs.insert(CmpR1); in collectIndRegsForLoop()
555 Rs.insert(CmpR2); in collectIndRegsForLoop()
559 dump_partition(dbgs(), Rs, *TRI); in collectIndRegsForLoop()
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H A DHexagonPseudo.td42 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
51 let Inst{27} = Rs;
209 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
210 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
211 bits<5> Rs;
217 let Inst{20-16} = Rs;
286 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
336 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
355 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
432 class Vsplatr_template : InstHexagon<(outs HvxVR:$Vd), (ins IntRegs:$Rs),
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H A DHexagonGenInsert.cpp129 RegisterSet &insert(const RegisterSet &Rs) { in insert()
130 return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); in insert()
132 RegisterSet &remove(const RegisterSet &Rs) { in remove()
133 return static_cast<RegisterSet&>(BitVector::reset(Rs)); in remove()
156 bool includes(const RegisterSet &Rs) const { in includes()
158 return !Rs.BitVector::test(*this); in includes()
160 bool intersects(const RegisterSet &Rs) const { in intersects()
161 return BitVector::anyCommon(Rs); in intersects()
1207 void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
1244 void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, in stats() argument
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/
H A DInProcessMemoryAccess.cpp66 ArrayRef<ExecutorAddr> Rs, OnReadUIntsCompleteFn<uint8_t> OnComplete) { in readUInt8sAsync() argument
68 Result.reserve(Rs.size()); in readUInt8sAsync()
69 for (auto &R : Rs) in readUInt8sAsync()
75 ArrayRef<ExecutorAddr> Rs, OnReadUIntsCompleteFn<uint16_t> OnComplete) { in readUInt16sAsync() argument
77 Result.reserve(Rs.size()); in readUInt16sAsync()
78 for (auto &R : Rs) in readUInt16sAsync()
84 ArrayRef<ExecutorAddr> Rs, OnReadUIntsCompleteFn<uint32_t> OnComplete) { in readUInt32sAsync() argument
86 Result.reserve(Rs.size()); in readUInt32sAsync()
87 for (auto &R : Rs) in readUInt32sAsync()
93 ArrayRef<ExecutorAddr> Rs, OnReadUIntsCompleteFn<uint64_t> OnComplete) { in readUInt64sAsync() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/
H A DMemoryAccess.h68 virtual void readUInt8sAsync(ArrayRef<ExecutorAddr> Rs,
71 virtual void readUInt16sAsync(ArrayRef<ExecutorAddr> Rs,
74 virtual void readUInt32sAsync(ArrayRef<ExecutorAddr> Rs,
77 virtual void readUInt64sAsync(ArrayRef<ExecutorAddr> Rs,
80 virtual void readPointersAsync(ArrayRef<ExecutorAddr> Rs,
83 virtual void readBuffersAsync(ArrayRef<ExecutorAddrRange> Rs,
86 virtual void readStringsAsync(ArrayRef<ExecutorAddr> Rs,
136 Expected<ReadUIntsResult<uint8_t>> readUInt8s(ArrayRef<ExecutorAddr> Rs) { in readUInt8s() argument
138 readUInt8sAsync(Rs, [&](Expected<ReadUIntsResult<uint8_t>> Result) { in readUInt8s()
144 Expected<ReadUIntsResult<uint16_t>> readUInt16s(ArrayRef<ExecutorAddr> Rs) { in readUInt16s() argument
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H A DEPCGenericMemoryAccess.h92 void readUInt8sAsync(ArrayRef<ExecutorAddr> Rs, in readUInt8sAsync() argument
104 Rs); in readUInt8sAsync()
107 void readUInt16sAsync(ArrayRef<ExecutorAddr> Rs, in readUInt16sAsync() argument
120 Rs); in readUInt16sAsync()
123 void readUInt32sAsync(ArrayRef<ExecutorAddr> Rs, in readUInt32sAsync() argument
136 Rs); in readUInt32sAsync()
139 void readUInt64sAsync(ArrayRef<ExecutorAddr> Rs, in readUInt64sAsync() argument
152 Rs); in readUInt64sAsync()
155 void readPointersAsync(ArrayRef<ExecutorAddr> Rs, in readPointersAsync() argument
168 Rs); in readPointersAsync()
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H A DInProcessMemoryAccess.h41 void readUInt8sAsync(ArrayRef<ExecutorAddr> Rs,
44 void readUInt16sAsync(ArrayRef<ExecutorAddr> Rs,
47 void readUInt32sAsync(ArrayRef<ExecutorAddr> Rs,
50 void readUInt64sAsync(ArrayRef<ExecutorAddr> Rs,
53 void readPointersAsync(ArrayRef<ExecutorAddr> Rs,
56 void readBuffersAsync(ArrayRef<ExecutorAddrRange> Rs,
59 void readStringsAsync(ArrayRef<ExecutorAddr> Rs,
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h26 operator Rs() { return Rs{rd + (shift ? 8 : 0)}; } in Rs() function
59 return LW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)}; in DecodeC_LWSP()
69 return LD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)}; in DecodeC_LDSP()
75 return SW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)}; in DecodeC_SWSP()
81 return SD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)}; in DecodeC_SDSP()
150 return B{rs1, Rs{0}, uint32_t(offset), 0b001}; in DecodeC_BNEZ()
151 return B{rs1, Rs{0}, uint32_t(int32_t(int16_t(offset | 0xfe00))), 0b001}; in DecodeC_BNEZ()
158 return B{rs1, Rs{0}, uint32_t(offset), 0b000}; in DecodeC_BEQZ()
159 return B{rs1, Rs{0}, uint32_t(int32_t(int16_t(offset | 0xfe00))), 0b000}; in DecodeC_BEQZ()
166 return ADDI{rd, Rs{0}, uint32_t(imm)}; in DecodeC_LI()
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H A DRISCVInstructions.h28 struct Rs { struct
46 Rs rs1; \ argument
52 Rs rs1; \
53 Rs rs2; \
68 Rs rs1; \
69 Rs rs2; \
75 Rs rs1; \
82 Rs rs1; \
88 Rs rs1; \
89 Rs rs2; \
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H A DEmulateInstructionRISCV.cpp133 std::optional<uint64_t> Rs::Read(EmulateInstructionRISCV &emulator) { in Read()
141 std::optional<int32_t> Rs::ReadI32(EmulateInstructionRISCV &emulator) { in ReadI32()
146 std::optional<int64_t> Rs::ReadI64(EmulateInstructionRISCV &emulator) { in ReadI64()
151 std::optional<uint32_t> Rs::ReadU32(EmulateInstructionRISCV &emulator) { in ReadU32()
156 std::optional<APFloat> Rs::ReadAPFloat(EmulateInstructionRISCV &emulator, in ReadAPFloat()
393 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, DecodeIImm(inst)}; in DecodeIType()
397 return T{Rs{DecodeRS1(inst)}, Rs{DecodeRS2(inst)}, DecodeBImm(inst), in DecodeBType()
402 return T{Rs{DecodeRS1(inst)}, Rs{DecodeRS2(inst)}, DecodeSImm(inst)}; in DecodeSType()
406 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, Rs{DecodeRS2(inst)}}; in DecodeRType()
410 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, DecodeRS2(inst)}; in DecodeRShamtType()
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/TargetProcess/
H A DOrcRTBootstrap.cpp65 [](std::vector<ExecutorAddr> Rs) { in readUIntsWrapper() argument
67 Result.reserve(Rs.size()); in readUIntsWrapper()
68 for (auto &R : Rs) in readUIntsWrapper()
81 [](std::vector<ExecutorAddr> Rs) { in readPointersWrapper() argument
83 Result.reserve(Rs.size()); in readPointersWrapper()
84 for (auto &R : Rs) in readPointersWrapper()
97 [](std::vector<ExecutorAddrRange> Rs) { in readBuffersWrapper() argument
99 Result.reserve(Rs.size()); in readBuffersWrapper()
100 for (auto &R : Rs) { in readBuffersWrapper()
115 [](std::vector<ExecutorAddr> Rs) { in readStringsWrapper() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
223 Rs = L.getOperand(1); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
268 CompoundInsn->addOperand(Rs); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp578 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
581 Rs))); in DecodeDAHIDATIMMR6()
583 Rs))); in DecodeDAHIDATIMMR6()
592 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
595 Rs))); in DecodeDAHIDATI()
597 Rs))); in DecodeDAHIDATI()
617 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
622 if (Rs >= Rt) { in DecodeAddiGroupBranch()
625 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
633 Rs))); in DecodeAddiGroupBranch()
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/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
43 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp155 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() argument
156 switch (Rs) { in DecodeSrcAddrMode()
183 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
185 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeI()
189 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
191 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeII()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DScalarEvolutionDivision.cpp151 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
163 Rs.push_back(R); in visitAddExpr()
168 Remainder = Rs[0]; in visitAddExpr()
173 Remainder = SE.getAddExpr(Rs); in visitAddExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1693 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1703 TmpInst.addOperand(Rs); in processInstruction()
1713 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1723 TmpInst.addOperand(Rs); in processInstruction()
1733 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1743 TmpInst.addOperand(Rs); in processInstruction()
1756 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1773 TmpInst.addOperand(Rs); in processInstruction()
1789 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1791 TmpInst.addOperand(Rs); in processInstruction()
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/freebsd/contrib/mandoc/
H A Dmandoc.css166 .Rs { font-style: normal;
277 .Ic, code.In, .Lb, .Lk, .Ms, .Mt, .Nd, code.Nm, .Pa, .Rs,
304 .Rs::before { content: "Rs"; }
319 .Pa::before, .Rs::before,
341 .Rs:hover::before, h2.Sh:hover::before, h3.Ss:hover::before, .St:hover::before,

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