Searched refs:RotateAmt (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Instructions.cpp | 2408 int RotateAmt = -1; in matchShuffleAsBitRotate() local
2417 if (0 <= RotateAmt && Offset != RotateAmt) in matchShuffleAsBitRotate()
2419 RotateAmt = Offset; in matchShuffleAsBitRotate()
2422 return RotateAmt; in matchShuffleAsBitRotate()
2427 unsigned MaxSubElts, unsigned &NumSubElts, unsigned &RotateAmt) { in isBitRotateMask() argument
2432 RotateAmt = EltRotateAmt * EltSizeInBits; in isBitRotateMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5116 SDValue RotateAmt = Val.getOperand(1); in tryAsSingleRLDCL() local
5117 if (RotateAmt.getOpcode() == ISD::Constant) in tryAsSingleRLDCL()
5122 SDValue Ops[] = {Val.getOperand(0), RotateAmt, getI32Imm(MB, dl)}; in tryAsSingleRLDCL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4948 MVT &RotateVT, unsigned &RotateAmt) { in isLegalBitRotate()
4956 NumElts, NumSubElts, RotateAmt)) in isLegalBitRotate()
4974 unsigned RotateAmt; in lowerVECTOR_SHUFFLEAsRotate()
4976 if (!isLegalBitRotate(SVN, DAG, Subtarget, RotateVT, RotateAmt)) in lowerVECTOR_SHUFFLEAsRotate()
4984 if (RotateVT.getScalarType() == MVT::i16 && RotateAmt == 8) in lowerVECTOR_SHUFFLEAsRotate()
4988 DAG.getConstant(RotateAmt, DL, RotateVT)); in lowerVECTOR_SHUFFLEAsRotate()
5014 unsigned RotateAmt; in lowerShuffleViaVRegSplitting()
5016 if (isLegalBitRotate(SVN, DAG, Subtarget, RotateVT, RotateAmt)) in lowerShuffleViaVRegSplitting()
4947 isLegalBitRotate(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,MVT & RotateVT,unsigned & RotateAmt) isLegalBitRotate() argument
4973 unsigned RotateAmt; lowerVECTOR_SHUFFLEAsRotate() local
5013 unsigned RotateAmt; lowerShuffleViaVRegSplitting() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | Instructions.h | 2278 unsigned &NumSubElts, unsigned &RotateAmt);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 11283 unsigned RotateAmt, NumSubElts; in matchShuffleAsBitRotate() local
11285 MaxSubElts, NumSubElts, RotateAmt)) in matchShuffleAsBitRotate()
11290 return RotateAmt; in matchShuffleAsBitRotate()
11306 int RotateAmt = matchShuffleAsBitRotate(RotateVT, VT.getScalarSizeInBits(), in lowerShuffleAsBitRotate() local
11308 if (RotateAmt < 0) in lowerShuffleAsBitRotate()
11315 if ((RotateAmt % 16) == 0) in lowerShuffleAsBitRotate()
11318 unsigned ShlAmt = RotateAmt; in lowerShuffleAsBitRotate()
11319 unsigned SrlAmt = RotateVT.getScalarSizeInBits() - RotateAmt; in lowerShuffleAsBitRotate()
11331 DAG.getTargetConstant(RotateAmt, DL, MVT::i8)); in lowerShuffleAsBitRotate()
38089 int RotateAmt = matchShuffleAsBitRotate(ShuffleVT, MaskScalarSizeInBits, in matchUnaryPermuteShuffle() local
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