Searched refs:RootDef (Results 1 – 3 of 3) sorted by relevance
355 MachineInstr *RootDef = MRI->getVRegDef(RootReg); in selectSExtBits() local357 if (RootDef->getOpcode() == TargetOpcode::G_SEXT_INREG && in selectSExtBits()358 RootDef->getOperand(2).getImm() == Bits) { in selectSExtBits()360 {[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }}}; in selectSExtBits()533 MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in renderVLOp() local535 if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) { in renderVLOp()536 auto C = RootDef->getOperand(1).getCImm(); in renderVLOp()558 MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectAddrRegImm() local559 if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) { in selectAddrRegImm()561 [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }, in selectAddrRegImm()[all …]
407 ComplexRendererFns tryFoldAddLowIntoImm(MachineInstr &RootDef, unsigned Size,7582 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeUnscaled() local7584 MachineOperand &OffImm = RootDef->getOperand(2); in selectAddrModeUnscaled()7597 MachineOperand &Base = RootDef->getOperand(1); in selectAddrModeUnscaled()7607 AArch64InstructionSelector::tryFoldAddLowIntoImm(MachineInstr &RootDef, in tryFoldAddLowIntoImm() argument7610 if (RootDef.getOpcode() != AArch64::G_ADD_LOW) in tryFoldAddLowIntoImm()7612 MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg()); in tryFoldAddLowIntoImm()7625 auto &MF = *RootDef.getParent()->getParent(); in tryFoldAddLowIntoImm()7630 MachineIRBuilder MIRBuilder(RootDef); in tryFoldAddLowIntoImm()7652 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeIndexed() local[all …]
5683 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectMUBUFScratchOffen() local5698 } else if (RootDef->getOpcode() == AMDGPU::G_FRAME_INDEX) { in selectMUBUFScratchOffen()5699 FI = RootDef->getOperand(1).getIndex(); in selectMUBUFScratchOffen()5920 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDS1Addr1OffsetImpl() local5933 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDS1Addr1OffsetImpl()5982 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDSReadWrite2Impl() local5997 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDSReadWrite2Impl()