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Searched refs:Rm (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td394 let Inst{6-3} = 0b1111; // Rm = pc
453 // ADD <Rm>, sp
465 // ADD sp, <Rm>
466 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
467 "add", "\t$Rdn, $Rm", []>,
470 bits<4> Rm;
472 let Inst{6-3} = Rm;
483 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
486 bits<4> Rm;
487 let Inst{6-3} = Rm;
[all …]
H A DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
524 bits<4> Rm;
527 let Inst{3-0} = Rm;
534 bits<4> Rm;
537 let Inst{3-0} = Rm;
544 bits<4> Rm;
547 let Inst{3-0} = Rm;
583 bits<4> Rm;
587 let Inst{3-0} = Rm;
[all …]
H A DARMInstrInfo.td1588 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1589 iir, opc, "\t$Rd, $Rn, $Rm",
1590 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1594 bits<4> Rm;
1600 let Inst{3-0} = Rm;
1661 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1662 iir, opc, "\t$Rd, $Rn, $Rm",
1667 bits<4> Rm;
1670 let Inst{3-0} = Rm;
1723 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
H A DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
632 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
637 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
638 "vld1", Dt, "$Vd, $Rn, $Rm",
649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
654 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
655 "vld1", Dt, "$Vd, $Rn, $Rm",
676 let Rm = 0b1111;
685 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
[all …]
H A DARMInstrCDE.td85 dag Rm;
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
155 bits<4> Rm;
160 let Inst{15-12} = Rm{3-0};
171 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
179 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
476 let Rm = (ins regclass:$Vm);
484 let Rm = (ins regclass:$Qm);
498 let Iops2 = !con(IOpsPrefix, ops.Rm);
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
22 // Rd after a minimum of three cycles after the result in Rm and Rs is available
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrFormats.td807 // {11-0} imm12/Rm
825 // {11-0} imm12/Rm
844 // {13} 1 == Rm, 0 == imm12
846 // {11-0} imm12/Rm
864 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
871 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
896 // {13} 1 == imm8, 0 == Rm
900 // {3-0} imm3_0/Rm
922 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
929 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
[all …]
H A DARMInstrMVE.td481 : MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
482 "$RdaSrc, $Rm", "@earlyclobber $RdaDest,$RdaDest = $RdaSrc",
485 (i32 rGPR:$RdaSrc), (i32 rGPR:$Rm))))]> {
486 bits<4> Rm;
488 let Inst{15-12} = Rm{3-0};
535 bits<4> Rm;
538 let Inst{15-12} = Rm{3-0};
554 iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
555 "$RdaLo, $RdaHi, $Rm", op5, 0b0, pattern> {
562 iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm, saturateop:$sat),
[all …]
H A DARMBaseInstrInfo.cpp3352 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3353 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3359 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3360 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3389 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3390 if (!Rm) in getNumMicroOpsSwiftLdSt()
3392 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3401 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3402 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3420 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td66 def : Pat<(relaxed_load<atomic_load_azext_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
68 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
69 def : Pat<(relaxed_load<atomic_load_azext_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
71 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
82 def : Pat<(relaxed_load<atomic_load_azext_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
84 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
85 def : Pat<(relaxed_load<atomic_load_azext_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
87 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
101 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)),
102 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]
H A DAArch64InstrFormats.td2153 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
2155 bits<5> Rm;
2159 let Inst{4-0} = Rm;
2479 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
2480 asm, "\t$Rd, $Rn, $Rm", "",
2481 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2485 bits<5> Rm;
2487 let Inst{20-16} = Rm;
2566 : I<(outs), (ins GPR64common:$Rm), asm, "\t$Rm", "", []>,
2568 bits<5> Rm;
[all …]
H A DAArch64InstrInfo.td1065 def AArch64addp : PatFrags<(ops node:$Rn, node:$Rm),
1066 [(AArch64addp_n node:$Rn, node:$Rm),
1067 (int_aarch64_neon_addp node:$Rn, node:$Rm)]>;
1074 def AArch64faddp : PatFrags<(ops node:$Rn, node:$Rm),
1075 [(AArch64addp_n node:$Rn, node:$Rm),
1076 (int_aarch64_neon_faddp node:$Rn, node:$Rm)]>;
1081 def AArch64facge : PatFrags<(ops node:$Rn, node:$Rm),
1082 [(AArch64fcmge (fabs node:$Rn), (fabs node:$Rm)),
1083 (int_aarch64_neon_facge node:$Rn, node:$Rm)]>;
1084 def AArch64facgt : PatFrags<(ops node:$Rn, node:$Rm),
[all …]
H A DSVEInstrFormats.td1793 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
1794 asm, "\t$Zdn, $Rm",
1797 bits<5> Rm;
1802 let Inst{9-5} = Rm;
5833 : I<(outs), (ins rt:$Rn, rt:$Rm),
5834 asm, "\t$Rn, $Rm",
5837 bits<5> Rm;
5842 let Inst{20-16} = Rm;
5854 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
5855 asm, "\t$Pd, $Rn, $Rm",
[all …]
H A DAArch64InstrGISel.td480 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
482 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
485 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
487 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
H A DAArch64SchedPredicates.td298 // MOV Rd, Rm =>
299 // ORR Rd, ZR, Rm, LSL #0
H A DSMEInstrFormats.td803 bits<5> Rm;
811 let Inst{20-16} = Rm;
827 gpr_ty:$Rm),
828 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
834 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
835 …tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
980 bits<5> Rm;
988 let Inst{20-16} = Rm;
1005 GPR64sp:$Rn, gpr_ty:$Rm),
1006 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1672 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1677 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1710 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
2055 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2160 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
2186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
2218 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
2251 if (type && Rm == 15) in DecodeAddrMode3Instruction()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1288 uint32_t Rm; // the source register in EmulateMOVRdRm() local
1294 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
1301 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
1308 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1311 if (setflags && (BadReg(Rd) || BadReg(Rm))) in EmulateMOVRdRm()
1315 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) in EmulateMOVRdRm()
1320 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1331 uint32_t result = ReadCoreReg(Rm, &success); in EmulateMOVRdRm()
1339 else if (Rd == GetFramePointerRegisterNumber() && Rm == 13) in EmulateMOVRdRm()
1344 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm); in EmulateMOVRdRm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp655 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
685 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeThreeAddrSRegInstruction()
709 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeThreeAddrSRegInstruction()
1334 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1350 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1359 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1368 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1377 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1386 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1395 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
[all …]
/freebsd/sys/arm64/arm64/
H A Dundefined.c187 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
205 Rm = (insn & 0xf); in swp_emulate()
209 val = regs[Rm]; in swp_emulate()
/freebsd/crypto/openssl/test/certs/
H A Dbadalt8-key.pem5 PQPxnY2uLSRcMZ7n6FuAs+Rm+eHS+8kKTsARDaKo7g2l7i4egPHcZc2jYlvoEo1/
/freebsd/crypto/openssl/demos/sslecho/
H A Dcert.pem31 4gKT+/h3Ep1Ut73daskFAvNJFFt/5Rm+xZECHrxRkXqW1AN/2eXX
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp930 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue() local
931 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1284 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue() local
1301 uint32_t Binary = Rm; in getLdStSORegOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp862 MCRegister Rm = MI->getOperand(2).getReg(); in printRangePrefetchAlias() local
865 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) in printRangePrefetchAlias()
866 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, in printRangePrefetchAlias()
886 O << getRegisterName(Rm); in printRangePrefetchAlias()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp963 int Rn = 0, Rm = 0; in buildHvxVectorReg() local
977 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
981 Rm = 0; in buildHvxVectorReg()
984 Rm += 4; in buildHvxVectorReg()
988 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()

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