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Searched refs:Rm (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td395 let Inst{6-3} = 0b1111; // Rm = pc
454 // ADD <Rm>, sp
466 // ADD sp, <Rm>
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
468 "add", "\t$Rdn, $Rm", []>,
471 bits<4> Rm;
473 let Inst{6-3} = Rm;
484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
487 bits<4> Rm;
488 let Inst{6-3} = Rm;
[all …]
H A DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
524 bits<4> Rm;
527 let Inst{3-0} = Rm;
534 bits<4> Rm;
537 let Inst{3-0} = Rm;
544 bits<4> Rm;
547 let Inst{3-0} = Rm;
583 bits<4> Rm;
587 let Inst{3-0} = Rm;
[all …]
H A DARMInstrInfo.td1569 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1570 iir, opc, "\t$Rd, $Rn, $Rm",
1571 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1575 bits<4> Rm;
1581 let Inst{3-0} = Rm;
1642 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1643 iir, opc, "\t$Rd, $Rn, $Rm",
1648 bits<4> Rm;
1651 let Inst{3-0} = Rm;
1704 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
H A DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
632 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
637 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
638 "vld1", Dt, "$Vd, $Rn, $Rm",
649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
654 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
655 "vld1", Dt, "$Vd, $Rn, $Rm",
676 let Rm = 0b1111;
685 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
[all …]
H A DARMInstrCDE.td85 dag Rm;
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
155 bits<4> Rm;
160 let Inst{15-12} = Rm{3-0};
171 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
179 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
476 let Rm = (ins regclass:$Vm);
484 let Rm = (ins regclass:$Qm);
498 let Iops2 = !con(IOpsPrefix, ops.Rm);
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
22 // Rd after a minimum of three cycles after the result in Rm and Rs is available
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrFormats.td815 // {11-0} imm12/Rm
833 // {11-0} imm12/Rm
852 // {13} 1 == Rm, 0 == imm12
854 // {11-0} imm12/Rm
872 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
879 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
904 // {13} 1 == imm8, 0 == Rm
908 // {3-0} imm3_0/Rm
930 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
937 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
[all …]
H A DARMInstrMVE.td480 : MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
481 "$RdaSrc, $Rm", "@earlyclobber $RdaDest,$RdaDest = $RdaSrc",
484 (i32 rGPR:$RdaSrc), (i32 rGPR:$Rm))))]> {
485 bits<4> Rm;
487 let Inst{15-12} = Rm{3-0};
534 bits<4> Rm;
537 let Inst{15-12} = Rm{3-0};
553 iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
554 "$RdaLo, $RdaHi, $Rm", op5, 0b0, pattern> {
561 iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm, saturateo
[all...]
H A DARMBaseInstrInfo.cpp3509 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3510 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3516 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3517 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3546 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3547 if (!Rm) in getNumMicroOpsSwiftLdSt()
3549 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3558 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3559 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3577 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td66 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
68 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
69 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
71 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
82 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
84 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
85 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
87 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
98 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
100 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]
H A DAArch64InstrFormats.td2032 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
2034 bits<5> Rm;
2038 let Inst{4-0} = Rm;
2347 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
2348 asm, "\t$Rd, $Rn, $Rm", "",
2349 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2353 bits<5> Rm;
2355 let Inst{20-16} = Rm;
2434 : I<(outs), (ins GPR64common:$Rm), asm, "\t$Rm", "", []>,
2436 bits<5> Rm;
[all …]
H A DAArch64InstrInfo.td876 def AArch64addp : PatFrags<(ops node:$Rn, node:$Rm),
877 [(AArch64addp_n node:$Rn, node:$Rm),
878 (int_aarch64_neon_addp node:$Rn, node:$Rm)]>;
885 def AArch64faddp : PatFrags<(ops node:$Rn, node:$Rm),
886 [(AArch64addp_n node:$Rn, node:$Rm),
887 (int_aarch64_neon_faddp node:$Rn, node:$Rm)]>;
892 def AArch64facge : PatFrags<(ops node:$Rn, node:$Rm),
893 [(AArch64fcmge (fabs node:$Rn), (fabs node:$Rm)),
894 (int_aarch64_neon_facge node:$Rn, node:$Rm)]>;
895 def AArch64facgt : PatFrags<(ops node:$Rn, node:$Rm),
[all …]
H A DSVEInstrFormats.td1658 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
1659 asm, "\t$Zdn, $Rm",
1662 bits<5> Rm;
1667 let Inst{9-5} = Rm;
5335 : I<(outs), (ins rt:$Rn, rt:$Rm),
5336 asm, "\t$Rn, $Rm",
5339 bits<5> Rm;
5344 let Inst{20-16} = Rm;
5356 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
5357 asm, "\t$Pd, $Rn, $Rm",
[all …]
H A DAArch64InstrGISel.td537 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
539 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
542 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
544 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
H A DSMEInstrFormats.td506 bits<5> Rm;
514 let Inst{20-16} = Rm;
530 gpr_ty:$Rm),
531 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
537 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
538 …tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
683 bits<5> Rm;
691 let Inst{20-16} = Rm;
708 GPR64sp:$Rn, gpr_ty:$Rm),
709 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
[all …]
H A DAArch64SchedPredicates.td298 // MOV Rd, Rm =>
299 // ORR Rd, ZR, Rm, LSL #0
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1667 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1672 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1705 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1710 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
2049 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2154 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
2180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
2212 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
2245 if (type && Rm == 15) in DecodeAddrMode3Instruction()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1288 uint32_t Rm; // the source register in EmulateMOVRdRm() local
1294 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
1301 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
1308 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1311 if (setflags && (BadReg(Rd) || BadReg(Rm))) in EmulateMOVRdRm()
1315 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) in EmulateMOVRdRm()
1320 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1331 uint32_t result = ReadCoreReg(Rm, &success); in EmulateMOVRdRm()
1339 else if (Rd == GetFramePointerRegisterNumber() && Rm == 13) in EmulateMOVRdRm()
1344 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm); in EmulateMOVRdRm()
[all …]
/freebsd/sys/arm64/arm64/
H A Dundefined.c206 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
225 Rm = (insn & 0xf); in swp_emulate()
229 val = regs[Rm]; in swp_emulate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp606 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
636 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeThreeAddrSRegInstruction()
660 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeThreeAddrSRegInstruction()
1258 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1274 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1283 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1292 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1301 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1310 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
1319 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr, in DecodeAddSubERegInstruction()
[all …]
/freebsd/crypto/openssl/test/certs/
H A Dbadalt8-key.pem5 PQPxnY2uLSRcMZ7n6FuAs+Rm+eHS+8kKTsARDaKo7g2l7i4egPHcZc2jYlvoEo1/
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp863 unsigned Rm = MI->getOperand(2).getReg(); in printRangePrefetchAlias()
865 // "Rm" must be a 64-bit GPR for RPRFM. in printRangePrefetchAlias()
866 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) in printRangePrefetchAlias()
867 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, in printRangePrefetchAlias()
887 O << getRegisterName(Rm); in printSysAlias()
848 unsigned Rm = MI->getOperand(2).getReg(); printRangePrefetchAlias() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp917 // [Rn, Rm] in getThumbAdrLabelOpValue()
918 // {5-3} = Rm in getThumbAdrLabelOpValue()
923 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
924 return (Rm << 3) | Rn;
1277 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getHiLoImmOpValue()
1290 // {3-0} = Rm in getLdStSORegOpValue()
1294 uint32_t Binary = Rm; in getLdStSORegOpValue()
1307 // {13} 1 == imm12, 0 == Rm in getLdStSORegOpValue()
1309 // {11-0} imm12/Rm in getLdStSORegOpValue()
1316 // if reg +/- reg, Rm wil in getAddrMode2OffsetOpValue()
934 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); getThumbAddrModeRegRegOpValue() local
1288 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); getLdStSORegOpValue() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp950 // Construct two halves in parallel, then or them together. Rn and Rm count in buildHvxVectorReg()
953 int Rn = 0, Rm = 0; in buildHvxVectorReg()
967 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
971 Rm = 0; in buildHvxVectorReg()
974 Rm += 4; in buildHvxVectorReg()
978 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
954 int Rn = 0, Rm = 0; buildHvxVectorReg() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td1303 (instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"),

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