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Searched refs:ResultReg (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp362 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
364 ResultReg) in fastMaterializeAlloca()
368 return ResultReg; in fastMaterializeAlloca()
385 Register ResultReg = createResultReg(RC); in materializeInt() local
387 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
388 return ResultReg; in materializeInt()
421 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
423 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
426 return ResultReg; in materializeFP()
439 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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H A DAArch64PointerAuth.cpp410 Register ResultReg = MBBI->getOperand(0).getReg(); in expandPAuthBlend() local
413 emitBlend(MBBI, ResultReg, AddrDisc, IntDisc); in expandPAuthBlend()
H A DAArch64InstrInfo.cpp6667 Register ResultReg = Root.getOperand(0).getReg(); in genFusedMultiply() local
6684 if (ResultReg.isVirtual()) in genFusedMultiply()
6685 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
6695 MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
6700 MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
6706 MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
6732 Register ResultReg = Root.getOperand(0).getReg(); in genFNegatedMAD() local
6739 if (ResultReg.isVirtual()) in genFNegatedMAD()
6740 MRI.constrainRegClass(ResultReg, RC); in genFNegatedMAD()
6749 BuildMI(MF, MIMetadata(Root), TII->get(Opc), ResultReg) in genFNegatedMAD()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp79 unsigned &ResultReg, unsigned Alignment = 1);
87 unsigned &ResultReg);
317 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
466 ResultReg = createResultReg(RC); in X86FastEmitLoad()
468 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg); in X86FastEmitLoad()
701 unsigned &ResultReg) { in X86FastEmitExtend() argument
706 ResultReg = RR; in X86FastEmitExtend()
1349 unsigned ResultReg = 0; in X86SelectLoad() local
1350 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1354 updateValueMap(I, ResultReg); in X86SelectLoad()
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H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr);
324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
325 if (!ResultReg) in emitLogicalOp()
328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
329 return ResultReg; in emitLogicalOp()
340 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca() local
342 ResultReg) in fastMaterializeAlloca()
345 return ResultReg; in fastMaterializeAlloca()
361 Register ResultReg = createResultReg(RC); in materialize32BitInt() local
365 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp474 Register ResultReg = in selectBinaryOp() local
477 if (!ResultReg) in selectBinaryOp()
481 updateValueMap(I, ResultReg); in selectBinaryOp()
507 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp() local
509 if (!ResultReg) in selectBinaryOp()
513 updateValueMap(I, ResultReg); in selectBinaryOp()
522 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
524 if (!ResultReg) in selectBinaryOp()
530 updateValueMap(I, ResultReg); in selectBinaryOp()
806 CLI.ResultReg = createResultReg(TLI.getRegClassFor(ValueType)); in selectPatchpoint()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp598 Register ResultReg = createResultReg(MRI.getRegClass(Reg)); in copyValue() local
600 ResultReg) in copyValue()
602 return ResultReg; in copyValue()
610 Register ResultReg = in fastMaterializeAlloca() local
615 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
617 return ResultReg; in fastMaterializeAlloca()
629 Register ResultReg = in fastMaterializeConstant() local
634 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeConstant()
636 return ResultReg; in fastMaterializeConstant()
731 Register ResultReg = createResultReg(RC); in fastLowerArguments() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp190 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
299 Register ResultReg = createResultReg(RC); in fastEmitInst_r() local
307 ResultReg).addReg(Op0)); in fastEmitInst_r()
312 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
315 return ResultReg; in fastEmitInst_r()
321 Register ResultReg = createResultReg(RC); in fastEmitInst_rr() local
331 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg) in fastEmitInst_rr()
339 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
342 return ResultReg; in fastEmitInst_rr()
348 Register ResultReg = createResultReg(RC); in fastEmitInst_ri() local
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H A DARMInstructionSelector.cpp690 auto ResultReg = MIB.getReg(0); in selectGlobal() local
698 .addDef(ResultReg) in selectGlobal()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp160 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
430 Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
432 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
433 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
448 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in PPCEmitLoad() argument
463 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
519 if (ResultReg == 0) in PPCEmitLoad()
520 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
535 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in PPCEmitLoad()
543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in PPCEmitLoad()
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H A DPPCRegisterInfo.cpp593 Register ResultReg; in getRegAllocationHints() local
597 ResultReg = ResultOp->getReg(); in getRegAllocationHints()
598 if (ResultReg.isVirtual() && in getRegAllocationHints()
599 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && in getRegAllocationHints()
600 VRM->hasPhys(ResultReg)) { in getRegAllocationHints()
601 Register UACCPhys = VRM->getPhys(ResultReg); in getRegAllocationHints()
618 ResultReg = ResultOp->getReg(); in getRegAllocationHints()
619 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && in getRegAllocationHints()
620 VRM->hasPhys(ResultReg)) { in getRegAllocationHints()
621 Register ACCPhys = VRM->getPhys(ResultReg); in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1066 Register ResultReg = I.getOperand(0).getReg(); in selectFCmp() local
1068 ResultReg, in selectFCmp()
1069 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
1083 TII.get(SETFOpc[2]), ResultReg) in selectFCmp()
1110 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); in selectFCmp()
1655 unsigned ResultReg; // Register containing the desired result. in selectMulDivRem() member
1803 if (OpEntry.ResultReg == X86::AH && STI.is64Bit()) { in selectMulDivRem()
1822 .addReg(OpEntry.ResultReg); in selectMulDivRem()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp2453 Register ResultReg = in eliminateFrameIndex() local
2461 auto Shift = BuildMI(*MBB, MI, DL, TII->get(OpCode), ResultReg); in eliminateFrameIndex()
2475 .addReg(ResultReg); in eliminateFrameIndex()
2476 ResultReg = NewDest; in eliminateFrameIndex()
2481 if ((MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) != in eliminateFrameIndex()
2484 Register ScaledReg = ResultReg; in eliminateFrameIndex()
2537 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg) in eliminateFrameIndex()
2540 ResultReg = ScaledReg; in eliminateFrameIndex()
2559 FIOp.ChangeToRegister(ResultReg, false, false, true); in eliminateFrameIndex()
H A DSIInstrInfo.cpp7518 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in moveScalarAddSub() local
7532 MRI.replaceRegWith(OldDstReg, ResultReg); in moveScalarAddSub()
7535 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in moveScalarAddSub()
7635 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
7644 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
7648 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
7649 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerScalarAbs()
8134 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
8146 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg); in splitScalar64BitBCNT()
8148 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
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H A DSIISelLowering.cpp4463 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
4481 .addReg(ResultReg) in emitLoadM0FromVGPRLoop()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h91 Register ResultReg; member
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp852 for (unsigned ResultReg : ResultRegs) in buildIntrinsic() local
853 MIB.addDef(ResultReg); in buildIntrinsic()
H A DLegalizerHelper.cpp1866 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1Reg).getReg(0); in widenScalarMergeValues() local
1881 MIRBuilder.buildOr(NextResult, ResultReg, Shl); in widenScalarMergeValues()
1882 ResultReg = NextResult; in widenScalarMergeValues()
1886 MIRBuilder.buildTrunc(DstReg, ResultReg); in widenScalarMergeValues()
1888 MIRBuilder.buildIntToPtr(DstReg, ResultReg); in widenScalarMergeValues()
7455 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues() local
7468 MIRBuilder.buildOr(NextResult, ResultReg, Shl); in lowerMergeValues()
7469 ResultReg = NextResult; in lowerMergeValues()
7479 MIRBuilder.buildIntToPtr(DstReg, ResultReg); in lowerMergeValues()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp1282 Register ResultReg = Call->ReturnRegister; in generateKernelClockInst() local
1283 MRI->setRegClass(ResultReg, &SPIRV::IDRegClass); in generateKernelClockInst()
1294 .addDef(ResultReg) in generateKernelClockInst()