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Searched refs:ResultReg (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp354 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
356 ResultReg) in fastMaterializeAlloca()
360 return ResultReg; in fastMaterializeAlloca()
377 Register ResultReg = createResultReg(RC); in materializeInt() local
379 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
380 return ResultReg; in materializeInt()
413 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
415 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
418 return ResultReg; in materializeFP()
431 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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H A DAArch64InstrInfo.cpp7463 Register ResultReg = Root.getOperand(0).getReg(); in genFusedMultiply() local
7480 if (ResultReg.isVirtual()) in genFusedMultiply()
7481 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
7491 MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
7496 MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
7502 MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
7528 Register ResultReg = Root.getOperand(0).getReg(); in genFNegatedMAD() local
7535 if (ResultReg.isVirtual()) in genFNegatedMAD()
7536 MRI.constrainRegClass(ResultReg, RC); in genFNegatedMAD()
7545 BuildMI(MF, MIMetadata(Root), TII->get(Opc), ResultReg) in genFNegatedMAD()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp79 Register &ResultReg, unsigned Alignment = 1);
87 Register &ResultReg);
318 MachineMemOperand *MMO, Register &ResultReg, in X86FastEmitLoad() argument
467 ResultReg = createResultReg(RC); in X86FastEmitLoad()
469 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg); in X86FastEmitLoad()
701 EVT SrcVT, Register &ResultReg) { in X86FastEmitExtend() argument
706 ResultReg = RR; in X86FastEmitExtend()
1348 Register ResultReg; in X86SelectLoad() local
1349 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1353 updateValueMap(I, ResultReg); in X86SelectLoad()
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H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp179 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr);
322 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
323 if (!ResultReg) in emitLogicalOp()
326 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
327 return ResultReg; in emitLogicalOp()
338 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca() local
340 ResultReg) in fastMaterializeAlloca()
343 return ResultReg; in fastMaterializeAlloca()
359 Register ResultReg = createResultReg(RC); in materialize32BitInt() local
363 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp471 Register ResultReg = in selectBinaryOp() local
474 if (!ResultReg) in selectBinaryOp()
478 updateValueMap(I, ResultReg); in selectBinaryOp()
504 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp() local
506 if (!ResultReg) in selectBinaryOp()
510 updateValueMap(I, ResultReg); in selectBinaryOp()
519 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
521 if (!ResultReg) in selectBinaryOp()
527 updateValueMap(I, ResultReg); in selectBinaryOp()
803 CLI.ResultReg = createResultReg(TLI.getRegClassFor(ValueType)); in selectPatchpoint()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp604 Register ResultReg = createResultReg(MRI.getRegClass(Reg)); in copyValue() local
606 ResultReg) in copyValue()
608 return ResultReg; in copyValue()
616 Register ResultReg = in fastMaterializeAlloca() local
621 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
623 return ResultReg; in fastMaterializeAlloca()
635 Register ResultReg = in fastMaterializeConstant() local
640 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastMaterializeConstant()
642 return ResultReg; in fastMaterializeConstant()
737 Register ResultReg = createResultReg(RC); in fastLowerArguments() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp215 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
324 Register ResultReg = createResultReg(RC); in fastEmitInst_r() local
332 ResultReg).addReg(Op0)); in fastEmitInst_r()
337 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
340 return ResultReg; in fastEmitInst_r()
346 Register ResultReg = createResultReg(RC); in fastEmitInst_rr() local
356 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg) in fastEmitInst_rr()
364 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
367 return ResultReg; in fastEmitInst_rr()
373 Register ResultReg = createResultReg(RC); in fastEmitInst_ri() local
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H A DARMInstructionSelector.cpp690 auto ResultReg = MIB.getReg(0); in selectGlobal() local
698 .addDef(ResultReg) in selectGlobal()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp153 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
418 Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
420 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
421 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
436 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in PPCEmitLoad() argument
451 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
507 if (!ResultReg) in PPCEmitLoad()
508 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
523 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in PPCEmitLoad()
531 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in PPCEmitLoad()
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H A DPPCRegisterInfo.cpp587 Register ResultReg; in getRegAllocationHints() local
591 ResultReg = ResultOp->getReg(); in getRegAllocationHints()
592 if (ResultReg.isVirtual() && in getRegAllocationHints()
593 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && in getRegAllocationHints()
594 VRM->hasPhys(ResultReg)) { in getRegAllocationHints()
595 Register UACCPhys = VRM->getPhys(ResultReg); in getRegAllocationHints()
612 ResultReg = ResultOp->getReg(); in getRegAllocationHints()
613 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && in getRegAllocationHints()
614 VRM->hasPhys(ResultReg)) { in getRegAllocationHints()
615 Register ACCPhys = VRM->getPhys(ResultReg); in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizerCombiner.cpp82 Register ResultReg = MI.getOperand(0).getReg(); in applySPIRVDistance() local
91 .addDef(ResultReg) // Result register in applySPIRVDistance()
H A DSPIRVBuiltins.cpp1442 Register ResultReg = Call->ReturnRegister; in generateKernelClockInst() local
1453 .addDef(ResultReg) in generateKernelClockInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp3091 Register ResultReg = in eliminateFrameIndex() local
3099 Register TmpResultReg = ResultReg; in eliminateFrameIndex()
3117 MF->getRegInfo().constrainRegClass(ResultReg, in eliminateFrameIndex()
3119 NewDest = ResultReg; in eliminateFrameIndex()
3126 ResultReg = NewDest; in eliminateFrameIndex()
3131 if ((MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) != in eliminateFrameIndex()
3134 Register ScaledReg = ResultReg; in eliminateFrameIndex()
3179 ? ResultReg in eliminateFrameIndex()
3204 BuildMI(*MBB, *Add, DL, TII->get(AMDGPU::S_MOV_B32), ResultReg) in eliminateFrameIndex()
3206 Add.addReg(ResultReg, RegState::Kill) in eliminateFrameIndex()
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H A DSIInstrInfo.cpp8010 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in moveScalarAddSub() local
8024 MRI.replaceRegWith(OldDstReg, ResultReg); in moveScalarAddSub()
8027 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in moveScalarAddSub()
8126 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
8135 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
8139 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
8140 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerScalarAbs()
8625 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
8637 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg); in splitScalar64BitBCNT()
8639 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
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H A DSIISelLowering.cpp4679 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
4698 .addReg(ResultReg) in emitLoadM0FromVGPRLoop()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1106 Register ResultReg = I.getOperand(0).getReg(); in selectFCmp() local
1108 ResultReg, in selectFCmp()
1109 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
1123 TII.get(SETFOpc[2]), ResultReg) in selectFCmp()
1150 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); in selectFCmp()
1695 unsigned ResultReg; // Register containing the desired result. in selectMulDivRem() member
1843 if (OpEntry.ResultReg == X86::AH && STI.is64Bit()) { in selectMulDivRem()
1862 .addReg(OpEntry.ResultReg); in selectMulDivRem()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h91 Register ResultReg; member
H A DTargetInstrInfo.h1323 Register ResultReg) const;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp876 for (Register ResultReg : ResultRegs) in buildIntrinsic() local
877 MIB.addDef(ResultReg); in buildIntrinsic()
H A DLegalizerHelper.cpp2165 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1Reg).getReg(0); in widenScalarMergeValues() local
2180 MIRBuilder.buildOr(NextResult, ResultReg, Shl); in widenScalarMergeValues()
2181 ResultReg = NextResult; in widenScalarMergeValues()
2185 MIRBuilder.buildTrunc(DstReg, ResultReg); in widenScalarMergeValues()
2187 MIRBuilder.buildIntToPtr(DstReg, ResultReg); in widenScalarMergeValues()
8376 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues() local
8389 MIRBuilder.buildOr(NextResult, ResultReg, Shl); in lowerMergeValues()
8390 ResultReg = NextResult; in lowerMergeValues()
8400 MIRBuilder.buildIntToPtr(DstReg, ResultReg); in lowerMergeValues()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1083 Register ResultReg) const { in reduceAccumulatorTree()
1097 Dest = ResultReg; in reduceAccumulatorTree()