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Searched refs:ReleaseAtCycles (Results 1 – 25 of 37) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td97 let ReleaseAtCycles = Res;
105 let ReleaseAtCycles = !listconcat([1], Res);
429 let ReleaseAtCycles = [2];
499 let ReleaseAtCycles = [3];
504 let ReleaseAtCycles = [3,1];
511 let ReleaseAtCycles = [4,3,1,1];
516 let ReleaseAtCycles = [4,3,1,1,1];
523 let ReleaseAtCycles = [3];
528 let ReleaseAtCycles = [3,1];
535 let ReleaseAtCycles = [4,3,1];
[all …]
H A DX86SchedBroadwell.td98 let ReleaseAtCycles = Res;
106 let ReleaseAtCycles = !listconcat([1], Res);
494 let ReleaseAtCycles = [2];
516 let ReleaseAtCycles = [3];
521 let ReleaseAtCycles = [3,1];
528 let ReleaseAtCycles = [4,3,1,1];
533 let ReleaseAtCycles = [4,3,1,1,1];
540 let ReleaseAtCycles = [3];
545 let ReleaseAtCycles = [3,1];
552 let ReleaseAtCycles = [4,3,1];
[all …]
H A DX86SchedHaswell.td103 let ReleaseAtCycles = Res;
111 let ReleaseAtCycles = !listconcat([1], Res);
492 let ReleaseAtCycles = [2];
515 let ReleaseAtCycles = [3];
520 let ReleaseAtCycles = [3,1];
527 let ReleaseAtCycles = [4,3,1,1];
532 let ReleaseAtCycles = [4,3,1,1,1];
539 let ReleaseAtCycles = [3];
544 let ReleaseAtCycles = [3,1];
551 let ReleaseAtCycles = [4,3,1];
[all …]
H A DX86SchedSkylakeServer.td97 let ReleaseAtCycles = Res;
105 let ReleaseAtCycles = !listconcat([1], Res);
430 let ReleaseAtCycles = [2];
495 let ReleaseAtCycles = [3];
500 let ReleaseAtCycles = [3,1];
507 let ReleaseAtCycles = [4,3,1,1];
512 let ReleaseAtCycles = [4,3,1,1,1];
519 let ReleaseAtCycles = [3];
524 let ReleaseAtCycles = [3,1];
531 let ReleaseAtCycles = [4,3,1];
[all …]
H A DX86SchedIceLake.td104 let ReleaseAtCycles = Res;
112 let ReleaseAtCycles = !listconcat([1], Res);
435 let ReleaseAtCycles = [2];
500 let ReleaseAtCycles = [3];
505 let ReleaseAtCycles = [3,1];
512 let ReleaseAtCycles = [4,3,1,1];
517 let ReleaseAtCycles = [4,3,1,1,1];
524 let ReleaseAtCycles = [3];
529 let ReleaseAtCycles = [3,1];
536 let ReleaseAtCycles = [4,3,1];
[all …]
H A DX86SchedSapphireRapids.td105 let ReleaseAtCycles = Res;
113 let ReleaseAtCycles = !listconcat([1], Res);
308 let ReleaseAtCycles = [7, 1];
527 let ReleaseAtCycles = [2, 1, 1, 1, 1];
548 let ReleaseAtCycles = [2, 1, 1, 1, 1];
645 let ReleaseAtCycles = [1, 2];
733 let ReleaseAtCycles = [5, 2, 1, 1];
746 let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
812 let ReleaseAtCycles = [2, 1];
819 let ReleaseAtCycles = [6, 1, 3];
[all …]
H A DX86SchedAlderlakeP.td112 let ReleaseAtCycles = Res;
120 let ReleaseAtCycles = !listconcat([1], Res);
311 let ReleaseAtCycles = [7, 1];
526 let ReleaseAtCycles = [2, 1, 1, 1, 1];
549 let ReleaseAtCycles = [2, 1, 1, 1, 1];
607 let ReleaseAtCycles = [1, 2];
654 let ReleaseAtCycles = [5, 2, 1, 1];
667 let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
730 let ReleaseAtCycles = [2, 1];
737 let ReleaseAtCycles = [6, 1, 3];
[all …]
H A DX86ScheduleBdVer2.td195 let ReleaseAtCycles = Res;
268 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ReleaseAtCycles = [2]; }
271 def : WriteRes<WriteMove, [PdEX01]> { let ReleaseAtCycles = [2]; }
277 def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ReleaseAtCycles = [18]; }
311 let ReleaseAtCycles = [375];
319 def : WriteRes<WriteNop, [PdEX01]> { let ReleaseAtCycles = [2]; }
329 let ReleaseAtCycles = [3, 2, 1];
336 let ReleaseAtCycles = [88];
343 let ReleaseAtCycles = [2];
355 let ReleaseAtCycles = [3, 3];
[all …]
H A DX86ScheduleZnver4.td399 let ReleaseAtCycles = Res;
512 let ReleaseAtCycles = [3, 1];
526 let ReleaseAtCycles = [1, 1, 4];
533 let ReleaseAtCycles = [4, 1, 1];
543 let ReleaseAtCycles = [4];
554 let ReleaseAtCycles = [4];
561 let ReleaseAtCycles = [2];
568 let ReleaseAtCycles = [1];
578 let ReleaseAtCycles = [1, 1, 7, 1];
589 let ReleaseAtCycles = [1];
[all …]
H A DX86ScheduleZnver3.td402 let ReleaseAtCycles = Res;
501 let ReleaseAtCycles = [3, 1];
515 let ReleaseAtCycles = [1, 1, 4];
522 let ReleaseAtCycles = [4, 1, 1];
532 let ReleaseAtCycles = [4];
543 let ReleaseAtCycles = [4];
550 let ReleaseAtCycles = [2];
557 let ReleaseAtCycles = [1];
567 let ReleaseAtCycles = [1, 1, 7, 1];
578 let ReleaseAtCycles = [1];
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP600.td134 let ReleaseAtCycles = [1, 34];
138 let ReleaseAtCycles = [1, 19];
144 let ReleaseAtCycles = [1, 34];
148 let ReleaseAtCycles = [1, 19];
239 let ReleaseAtCycles = [1, 4];
243 let ReleaseAtCycles = [1, 17];
249 let ReleaseAtCycles = [1, 6];
253 let ReleaseAtCycles = [1, 17];
259 let ReleaseAtCycles = [1, 11];
263 let ReleaseAtCycles = [1, 32];
[all …]
H A DRISCVSchedSiFive7.td269 let ReleaseAtCycles = [1, 65];
273 let ReleaseAtCycles = [1, 33];
279 let ReleaseAtCycles = [1, 65];
283 let ReleaseAtCycles = [1, 33];
372 let Latency = 14, ReleaseAtCycles = [1, 13] in {
389 let ReleaseAtCycles = [1, 26]; }
391 let ReleaseAtCycles = [1, 26]; }
405 let ReleaseAtCycles = [1, 55]; }
407 let ReleaseAtCycles = [1, 55]; }
457 let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
[all …]
H A DRISCVSchedSiFiveP400.td81 let ReleaseAtCycles = [1, 34];
85 let ReleaseAtCycles = [1, 19];
91 let ReleaseAtCycles = [1, 34];
95 let ReleaseAtCycles = [1, 19];
187 let ReleaseAtCycles = [1, 18];
191 let ReleaseAtCycles = [1, 17];
197 let ReleaseAtCycles = [1, 18];
201 let ReleaseAtCycles = [1, 17];
207 let ReleaseAtCycles = [1, 32];
211 let ReleaseAtCycles = [1, 32];
H A DRISCVSchedRocket.td73 let ReleaseAtCycles = [34];
77 let ReleaseAtCycles = [33];
83 let ReleaseAtCycles = [34];
87 let ReleaseAtCycles = [33];
170 let Latency = 20, ReleaseAtCycles = [20] in {
177 let ReleaseAtCycles = [20]; }
179 let ReleaseAtCycles = [25]; }
H A DRISCVSchedSyntacoreSCR1.td58 let Latency = 33, ReleaseAtCycles = [33] in {
67 let Latency = 2, ReleaseAtCycles=[2] in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedExynosM4.td145 let ReleaseAtCycles = [2]; }
179 let ReleaseAtCycles = [2]; }
182 let ReleaseAtCycles = [12]; }
184 let ReleaseAtCycles = [21]; }
268 let ReleaseAtCycles = [6, 6]; }
271 let ReleaseAtCycles = [6, 6]; }
274 let ReleaseAtCycles = [9, 9]; }
277 let ReleaseAtCycles = [7, 7]; }
280 let ReleaseAtCycles = [6, 6]; }
283 let ReleaseAtCycles = [9, 9]; }
[all …]
H A DAArch64SchedExynosM5.td145 let ReleaseAtCycles = [2]; }
147 let ReleaseAtCycles = [2]; }
197 let ReleaseAtCycles = [2]; }
200 let ReleaseAtCycles = [10]; }
202 let ReleaseAtCycles = [16]; }
231 let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
238 let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
242 let ReleaseAtCycles = [1, 13]; }
246 let ReleaseAtCycles = [1, 13]; }
285 let ReleaseAtCycles = [7, 7]; }
[all …]
H A DAArch64SchedTSV110.td69 let ReleaseAtCycles = [12]; }
71 let ReleaseAtCycles = [20]; }
97 def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
149 def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ReleaseAtCycles …
175 def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ReleaseAtCycles…
177 def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ReleaseAtCycles…
179 def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ReleaseAtCycles…
181 def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles…
183 def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ReleaseAtCycles…
185 def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ReleaseAtCycles…
[all …]
H A DAArch64SchedA510.td77 def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ReleaseAtCycles = [2];} // …
81 let Latency = 8; let ReleaseAtCycles = [8];
84 let Latency = 16; let ReleaseAtCycles = [16];
97 let ReleaseAtCycles = [m];
130 let ReleaseAtCycles = [2]; }
132 let ReleaseAtCycles = [3]; }
134 let ReleaseAtCycles = [4]; }
136 let ReleaseAtCycles = [3]; }
138 let ReleaseAtCycles = [4]; }
157 let ReleaseAtCycles = [2];}
[all …]
H A DAArch64SchedOryon.td311 // 2 cycle on 2 of I0123 with ReleaseAtCycles
315 let ReleaseAtCycles = [2,2];
322 let ReleaseAtCycles = [2,2];
329 let ReleaseAtCycles = [2,2];
340 let ReleaseAtCycles = [2];
346 let ReleaseAtCycles = [2];
589 let ReleaseAtCycles = [4];
600 let ReleaseAtCycles = [2];
625 let ReleaseAtCycles = [2];
630 let ReleaseAtCycles = [2];
[all …]
H A DAArch64SchedNeoverseV2.td110 let ReleaseAtCycles = [12]; }
112 let ReleaseAtCycles = [20]; }
121 let ReleaseAtCycles = [2]; }
132 let ReleaseAtCycles = [7]; }
134 let ReleaseAtCycles = [2]; }
137 let ReleaseAtCycles = [2]; }
140 let ReleaseAtCycles = [2]; }
142 let ReleaseAtCycles = [11]; }
146 let ReleaseAtCycles = [8]; }
149 let ReleaseAtCycles = [8]; }
[all …]
H A DAArch64SchedNeoverseV1.td115 let ReleaseAtCycles = [5]; }
117 let ReleaseAtCycles = [5]; }
127 let ReleaseAtCycles = [7]; }
129 let ReleaseAtCycles = [7]; }
131 let ReleaseAtCycles = [10]; }
133 let ReleaseAtCycles = [7]; }
135 let ReleaseAtCycles = [7]; }
137 let ReleaseAtCycles = [7]; }
145 let ReleaseAtCycles = [7]; }
147 let ReleaseAtCycles = [7]; }
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp121 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
1003 RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles, in ExpandProcResources() argument
1005 assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition"); in ExpandProcResources()
1024 ReleaseAtCycles.push_back(ReleaseAtCycles[i]); in ExpandProcResources()
1041 ReleaseAtCycles.push_back(ReleaseAtCycles[i]); in ExpandProcResources()
1170 std::vector<int64_t> ReleaseAtCycles = in GenSchedClassTables() local
1178 if (!ReleaseAtCycles.empty() && in GenSchedClassTables()
1179 ReleaseAtCycles.size() != PRVec.size()) { in GenSchedClassTables()
1187 .concat(Twine(ReleaseAtCycles.size()))); in GenSchedClassTables()
1201 if (ReleaseAtCycles.empty()) { in GenSchedClassTables()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td168 let ReleaseAtCycles = [4] in
170 let ReleaseAtCycles = [8] in
173 let ReleaseAtCycles = [2] in
175 let ReleaseAtCycles = [4] in
177 let ReleaseAtCycles = [8] in
179 let ReleaseAtCycles = [16] in
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DBottleneckAnalysis.cpp615 unsigned ReleaseAtCycles = Distribution[I]; in printBottleneckHints() local
616 if (ReleaseAtCycles) { in printBottleneckHints()
617 double Frequency = (double)ReleaseAtCycles * 100 / TotalCycles; in printBottleneckHints()

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