Searched refs:RegX (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 377 Register RegX; in selectZExtBits() local
379 if (mi_match(RootReg, *MRI, m_GAnd(m_Reg(RegX), m_SpecificICst(Mask)))) { in selectZExtBits()
380 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}}; in selectZExtBits()
383 if (mi_match(RootReg, *MRI, m_GZExt(m_Reg(RegX))) && in selectZExtBits()
384 MRI->getType(RegX).getScalarSizeInBits() == Bits) in selectZExtBits()
385 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}}; in selectZExtBits()
505 Register RegX; in selectSHXADD_UWOp() local
508 m_OneNonDBGUse(m_GAnd(m_OneNonDBGUse(m_GShl(m_Reg(RegX), m_ICst(C2))), in selectSHXADD_UWOp()
519 .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) in selectSHXADD_UWOp()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1333 Register RegX = OpX.getReg(); in reassociateOps() local
1341 if (RegX.isVirtual()) in reassociateOps()
1342 MRI.constrainRegClass(RegX, RC); in reassociateOps()
1363 std::swap(RegX, RegY); in reassociateOps()
1416 MIB1.addReg(RegX, getKillRegState(KillX)); in reassociateOps()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 856 Register RegM11, RegM12, RegX, RegY, RegM21, RegM22, RegM31, RegM32, RegA11, in reassociateFMA() local
869 GetOperandInfo(Leaf->getOperand(AddOpIdx), RegX, KillX); in reassociateFMA()
871 GetOperandInfo(Leaf->getOperand(1), RegX, KillX); in reassociateFMA()
875 GetOperandInfo(Leaf->getOperand(1), RegX, KillX); in reassociateFMA()
919 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
929 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22); in reassociateFMA()
960 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
970 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22); in reassociateFMA()
1017 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
|