Searched refs:RegVal (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInst.h | 49 unsigned RegVal; member
71 return RegVal; in getReg()
77 RegVal = Reg; in setReg()
137 Op.RegVal = Reg; in createReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 335 unsigned RegVal = GPRDecoderTable[(Insn >> 4) & 0x1f]; in decodeLoadStore() local
343 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
350 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
397 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
407 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
422 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
428 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 571 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR4StridedRegisterClass()
572 return RegVal / Multiple; in EncodeZPR4StridedRegisterClass()
587 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in encodeMatrixIndexGPR32()
588 unsigned T = (RegVal & 0x10) >> 1; in encodeMatrixIndexGPR32()
589 unsigned Zt = RegVal & 0x7; in encodeMatrixIndexGPR32()
597 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in getImm8OptLsl()
598 unsigned T = (RegVal & 0x10) >> 2; in getImm8OptLsl()
599 unsigned Zt = RegVal & 0x3; in getImm8OptLsl()
542 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); EncodeRegAsMultipleOf() local
558 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); EncodeZPR2StridedRegisterClass() local
568 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); EncodeZPR4StridedRegisterClass() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 52 unsigned RegVal; member
76 return RegVal; in getReg()
101 Op.RegVal = Reg; in createReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1552 auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) { in parseMachineFunctionInfo() argument
1558 RegVal = TempReg; in parseMachineFunctionInfo()
1564 Register &RegVal) { in parseMachineFunctionInfo() argument
1565 return !RegName.Value.empty() && parseRegister(RegName, RegVal); in parseMachineFunctionInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4556 unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg); in tryParseVectorList() local
4560 Stride = (PrevRegVal < RegVal) ? (RegVal - PrevRegVal) in tryParseVectorList()
4561 : (RegVal + NumRegs - PrevRegVal); in tryParseVectorList()
4566 if (Stride == 0 || RegVal != ((PrevRegVal + Stride) % NumRegs)) in tryParseVectorList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 1649 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, FR.VReg, FR.VT); in forwardMustTailParameters() local
1652 Chain = DAG.getCopyToReg(Chain, DL, FR.VReg, RegVal); in forwardMustTailParameters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1036 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT); in LowerFormalArguments() local
1038 Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal); in LowerFormalArguments()
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