Searched refs:RegVal (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 584 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeRegMul_MinMax() local
585 assert(RegVal >= Min && RegVal <= Max && (RegVal & (Multiple - 1)) == 0); in EncodeRegMul_MinMax()
586 return (RegVal - Min) / Multiple; in EncodeRegMul_MinMax()
596 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZK() local
600 return (RegVal - 24); in EncodeZK()
605 return (RegVal - 20); in EncodeZK()
620 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR2StridedRegisterClass() local
621 unsigned T = (RegVal & 0x10) >> 1; in EncodeZPR2StridedRegisterClass()
622 unsigned Zt = RegVal & 0x7; in EncodeZPR2StridedRegisterClass()
630 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR4StridedRegisterClass() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInst.h | 53 unsigned RegVal; member
75 return RegVal; in getReg()
81 RegVal = Reg.id(); in setReg()
141 Op.RegVal = Reg.id(); in createReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 335 unsigned RegVal = GPRDecoderTable[(Insn >> 4) & 0x1f]; in decodeLoadStore() local
343 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
350 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
397 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
407 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
422 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
428 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 53 unsigned RegVal; member
77 return RegVal; in getReg()
102 Op.RegVal = Reg; in createReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1806 auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) { in parseMachineFunctionInfo() argument
1812 RegVal = TempReg; in parseMachineFunctionInfo()
1818 Register &RegVal) { in parseMachineFunctionInfo() argument
1819 return !RegName.Value.empty() && parseRegister(RegName, RegVal); in parseMachineFunctionInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 1680 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, FR.VReg, FR.VT); in forwardMustTailParameters() local
1683 Chain = DAG.getCopyToReg(Chain, DL, FR.VReg, RegVal); in forwardMustTailParameters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4687 unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg); in tryParseVectorList() local
4691 Stride = (PrevRegVal < RegVal) ? (RegVal - PrevRegVal) in tryParseVectorList()
4692 : (NumRegs - (PrevRegVal - RegVal)); in tryParseVectorList()
4697 if (Stride == 0 || RegVal != ((PrevRegVal + Stride) % NumRegs)) in tryParseVectorList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1037 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT); in LowerFormalArguments() local
1039 Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal); in LowerFormalArguments()
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