Searched refs:RegVTs (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenInstruction.cpp | 526 const std::vector<ValueTypeByHwMode> &RegVTs = in HasOneImplicitDefWithKnownVT() local
528 if (RegVTs.size() == 1 && RegVTs[0].isSimple()) in HasOneImplicitDefWithKnownVT()
529 return RegVTs[0].getSimple().SimpleTy; in HasOneImplicitDefWithKnownVT()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 738 SmallVector<MVT, 4> RegVTs; member
764 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); in append()
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| H A D | SelectionDAGBuilder.cpp | 850 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), in RegsForValue()
871 RegVTs.push_back(RegisterVT); in RegsForValue()
896 *DAG.getContext(), *CallConv, RegVTs[Value]) in getCopyFromRegs()
897 : RegVTs[Value]; in getCopyFromRegs()
979 *DAG.getContext(), *CallConv, RegVTs[Value]) in getCopyToRegs()
980 : RegVTs[Value]; in getCopyToRegs()
1047 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && in AddInlineAsmOperands()
1052 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); in AddInlineAsmOperands()
1062 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands()
1077 for (auto CountAndVT : zip_first(RegCount, RegVTs)) { in getRegsAndSizes()
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