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Searched refs:RegV (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp423 RegV, enumerator
820 Reg.Group = RegV; in parseRegister()
858 Group = RegV; in parseRegister()
883 case RegV: in parseRegister()
884 if (Reg.Group != RegV && Reg.Group != RegFP) in parseRegister()
967 else if (Reg.Group == RegV) { in parseAnyRegister()
1001 int64_t MaxRegNum = (Group == RegV) ? 31 : 15; in parseIntegerRegister()
1049 RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR; in parseAddress()
1120 if (Reg.Group == RegV) { in parseAddressRegister()
1221 if (!HaveReg1 || Reg1.Group != RegV) in parseAddress()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp9194 SDValue RegV = IsCZERO_NEZ ? FalseV : TrueV; in lowerSELECT() local
9198 SDValue XorOp = DAG.getNode(ISD::XOR, DL, VT, RegV, ConstVal); in lowerSELECT()
9207 SDValue SubOp = DAG.getNode(ISD::SUB, DL, VT, RegV, ConstVal); in lowerSELECT()