| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterPressure.cpp | 100 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
108 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
155 void RegPressureTracker::increaseRegPressure(Register RegUnit, in increaseRegPressure() argument
161 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
170 void RegPressureTracker::decreaseRegPressure(Register RegUnit, in decreaseRegPressure() argument
173 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
363 Register RegUnit = Pair.RegUnit; in initLiveThru() local
364 if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit)) in initLiveThru()
365 increaseSetPressure(LiveThruPressure, *MRI, RegUnit, in initLiveThru()
371 Register RegUnit) { in getRegLanes() argument
[all …]
|
| H A D | LiveRegMatrix.cpp | 179 MCRegister RegUnit) { in query() argument
180 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
|
| H A D | MachineCopyPropagation.cpp | 255 MachineInstr *findCopyForUnit(MCRegUnit RegUnit, in findCopyForUnit() argument
258 auto CI = Copies.find(RegUnit); in findCopyForUnit()
266 MachineInstr *findCopyDefViaUnit(MCRegUnit RegUnit, in findCopyDefViaUnit() argument
268 auto CI = Copies.find(RegUnit); in findCopyDefViaUnit()
|
| H A D | MachineTraceMetrics.cpp | 1148 TBI.LiveIns.push_back(LiveInReg(RU.RegUnit, RU.Cycle)); in computeInstrHeights()
1149 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RU.RegUnit, MTM.TRI) << '@' in computeInstrHeights()
|
| H A D | MachinePipeliner.cpp | 1312 auto Reg = Use.RegUnit; in computeLiveIn()
1399 UpdateTargetRegs(Use.RegUnit); in computeLastUses()
1410 auto Reg = Use.RegUnit; in computeLastUses()
1503 InsertReg(LiveRegSets[Iter], Def.RegUnit); in computeMaxSetPressure()
|
| H A D | MachineScheduler.cpp | 1363 Register Reg = P.RegUnit; in updatePressureDiffs()
1588 Register Reg = P.RegUnit; in computeCyclicCriticalPath()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 39 Register RegUnit; ///< Virtual register or register unit. member
42 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
43 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
159 void addPressureChange(Register RegUnit, bool IsDec,
307 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in insert()
320 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in erase()
542 void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
544 void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
565 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
566 LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
[all …]
|
| H A D | MachineRegisterInfo.h | 644 PSetIterator getPressureSets(Register RegUnit) const;
1248 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1250 if (RegUnit.isVirtual()) { in PSetIterator()
1251 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1255 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1256 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1277 MachineRegisterInfo::getPressureSets(Register RegUnit) const { in getPressureSets() argument
1278 return PSetIterator(RegUnit, this); in getPressureSets()
|
| H A D | MachineTraceMetrics.h | 75 unsigned RegUnit; member
80 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
82 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
|
| H A D | ScheduleDAGInstrs.h | 79 unsigned RegUnit; member
82 : SU(su), OpIdx(op), RegUnit(R) {} in PhysRegSUOper()
84 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
|
| H A D | TargetRegisterInfo.h | 458 bool hasRegUnit(MCRegister Reg, Register RegUnit) const { in hasRegUnit() argument
460 if (Register(Unit) == RegUnit) in hasRegUnit()
891 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
911 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
|
| H A D | LiveRegMatrix.h | 153 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 534 struct RegUnit { struct
552 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit() argument
603 SmallVector<RegUnit, 8> RegUnits;
737 RegUnit &RU = RegUnits.emplace_back();
749 RegUnit &RU = RegUnits.emplace_back(); in newRegUnit()
761 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
762 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
|
| H A D | CodeGenRegisters.cpp | 602 for (unsigned RegUnit : RegUnits) { in getWeight() local
603 Weight += RegBank.getRegUnit(RegUnit).Weight; in getWeight()
1156 const RegUnit &RU = RegBank.getRegUnit(*UnitI); in buildRegUnitSet()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 707 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
708 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
709 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
710 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 324 LiveRange &RegUnit = LIS->getRegUnit(Unit); in optimizeElseBranch() local
325 if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx))) in optimizeElseBranch()
|
| H A D | SIMachineScheduler.h | 468 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
476 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
|
| H A D | GCNRegPressure.cpp | 270 return RM.RegUnit == Reg; in collectVirtualRegUses()
404 LaneBitmask &LiveMask = LiveRegs[U.RegUnit]; in recede()
407 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI); in recede()
|
| H A D | SIRegisterInfo.h | 329 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
|
| H A D | SIMachineScheduler.cpp | 330 if (RegMaskPair.RegUnit.isVirtual()) in initRegPressure()
331 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
357 Register Reg = RegMaskPair.RegUnit; in initRegPressure()
|
| H A D | SIRegisterInfo.cpp | 3079 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
3082 if (RegPressureIgnoredUnits[RegUnit]) in getRegUnitPressureSets()
3085 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfDebug.cpp | 718 for (auto &RegUnit : ClobberedRegUnits) in interpretValues() local
719 if (TRI.hasRegUnit(Reg, RegUnit)) in interpretValues()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); in EmitRegUnitPressure()
|