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Searched refs:RegUnit (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterPressure.cpp96 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
104 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
151 void RegPressureTracker::increaseRegPressure(Register RegUnit, in increaseRegPressure() argument
157 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
166 void RegPressureTracker::decreaseRegPressure(Register RegUnit, in decreaseRegPressure() argument
169 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
359 Register RegUnit = Pair.RegUnit; in initLiveThru() local
360 if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit)) in initLiveThru()
361 increaseSetPressure(LiveThruPressure, *MRI, RegUnit, in initLiveThru()
367 Register RegUnit) { in getRegLanes() argument
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H A DLiveRegMatrix.cpp187 MCRegUnit RegUnit) { in query() argument
188 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
189 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
H A DMachineCopyPropagation.cpp325 MachineInstr *findCopyForUnit(MCRegUnit RegUnit, in findCopyForUnit() argument
328 auto CI = Copies.find(RegUnit); in findCopyForUnit()
336 MachineInstr *findCopyDefViaUnit(MCRegUnit RegUnit, in findCopyDefViaUnit() argument
338 auto CI = Copies.find(RegUnit); in findCopyDefViaUnit()
998 for (unsigned RegUnit : TRI->regunits(Reg)) { in ForwardCopyPropagateBlock() local
999 if (!PreservedRegUnits.test(RegUnit)) in ForwardCopyPropagateBlock()
1000 Tracker.clobberRegUnit(RegUnit, *TRI, *TII, UseCopyInstr); in ForwardCopyPropagateBlock()
1002 if (MaybeDead == Tracker.findCopyForUnit(RegUnit, *TRI)) { in ForwardCopyPropagateBlock()
H A DMachineTraceMetrics.cpp1176 TBI.LiveIns.push_back(LiveInReg(RU.RegUnit, RU.Cycle)); in computeInstrHeights()
1177 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RU.RegUnit, MTM.TRI) << '@' in computeInstrHeights()
H A DMachinePipeliner.cpp1565 auto Reg = Use.RegUnit; in computeLiveIn()
1616 UpdateTargetRegs(Use.RegUnit); in computeLastUses()
1627 auto Reg = Use.RegUnit; in computeLastUses()
1718 InsertReg(LiveRegSets[Iter], Def.RegUnit); in computeMaxSetPressure()
H A DMachineVerifier.cpp3055 all_of(TRI->regunits(Reg), [&](const MCRegUnit RegUnit) { in checkLiveness() argument
3057 RegUnit); in checkLiveness()
H A DMachineScheduler.cpp1605 Register Reg = P.RegUnit; in updatePressureDiffs()
1839 Register Reg = P.RegUnit; in computeCyclicCriticalPath()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h40 Register RegUnit; ///< Virtual register or register unit. member
43 VRegMaskOrUnit(Register RegUnit, LaneBitmask LaneMask) in VRegMaskOrUnit()
44 : RegUnit(RegUnit), LaneMask(LaneMask) {} in VRegMaskOrUnit()
160 LLVM_ABI void addPressureChange(Register RegUnit, bool IsDec,
310 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in insert()
323 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in erase()
544 LLVM_ABI void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
546 LLVM_ABI void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
568 LLVM_ABI LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
569 LLVM_ABI LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
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H A DMachineRegisterInfo.h636 PSetIterator getPressureSets(Register RegUnit) const;
1248 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1250 if (RegUnit.isVirtual()) { in PSetIterator()
1251 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1255 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1256 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1277 MachineRegisterInfo::getPressureSets(Register RegUnit) const { in getPressureSets() argument
1278 return PSetIterator(RegUnit, this); in getPressureSets()
H A DMachineTraceMetrics.h76 unsigned RegUnit; member
81 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
83 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
H A DScheduleDAGInstrs.h81 unsigned RegUnit; member
84 : SU(su), OpIdx(op), RegUnit(R) {} in PhysRegSUOper()
86 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
H A DTargetRegisterInfo.h471 bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const { in hasRegUnit() argument
472 return llvm::is_contained(regunits(Reg), RegUnit); in hasRegUnit()
938 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
958 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
H A DLiveRegMatrix.h164 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegUnit RegUnit);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp280 return RM.RegUnit == Reg; in collectVirtualRegUses()
293 auto &LI = LIS.getInterval(P.RegUnit); in collectVirtualRegUses()
310 bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, in getLanesWithProperty() argument
313 if (RegUnit.isVirtual()) { in getLanesWithProperty()
314 const LiveInterval &LI = LIS.getInterval(RegUnit); in getLanesWithProperty()
322 Result = TrackLaneMasks ? MRI.getMaxLaneMaskForVReg(RegUnit) in getLanesWithProperty()
329 const LiveRange *LR = LIS.getCachedRegUnit(RegUnit); in getLanesWithProperty()
494 LaneBitmask GCNRPTracker::getLastUsedLanes(Register RegUnit, in getLastUsedLanes() argument
497 LIS, *MRI, true, RegUnit, Pos.getBaseIndex(), LaneBitmask::getNone(), in getLastUsedLanes()
554 LaneBitmask &LiveMask = LiveRegs[U.RegUnit]; in recede()
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H A DSIOptimizeExecMaskingPreRA.cpp332 LiveRange &RegUnit = LIS->getRegUnit(Unit); in optimizeElseBranch() local
333 if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx))) in optimizeElseBranch()
H A DSIMachineScheduler.h468 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
476 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
H A DSIRegisterInfo.h364 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
H A DGCNRegPressure.h282 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
H A DSIMachineScheduler.cpp326 if (RegMaskPair.RegUnit.isVirtual()) in initRegPressure()
327 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
353 Register Reg = RegMaskPair.RegUnit; in initRegPressure()
H A DSIRegisterInfo.cpp3778 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
3781 if (RegPressureIgnoredUnits[RegUnit]) in getRegUnitPressureSets()
3784 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h563 struct RegUnit { struct
581 RegUnit() { Roots[0] = Roots[1] = nullptr; } in RegUnit() argument
633 SmallVector<RegUnit, 8> RegUnits;
773 RegUnit &RU = RegUnits.emplace_back();
785 RegUnit &RU = RegUnits.emplace_back(); in newRegUnit()
797 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
798 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
H A DCodeGenRegisters.cpp527 for (unsigned RegUnit : RegUnits) in getWeight() local
528 Weight += RegBank.getRegUnit(RegUnit).Weight; in getWeight()
1080 const RegUnit &RU = RegBank.getRegUnit(UnitI); in buildRegUnitSet()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h722 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
723 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
724 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
725 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp244 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); in EmitRegUnitPressure()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.cpp725 for (auto &RegUnit : ClobberedRegUnits) in interpretValues() local
726 if (TRI.hasRegUnit(Reg, RegUnit)) in interpretValues()