| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
| H A D | XtensaAsmParser.cpp | 591 XtensaRegisterType RegType, in parseRegister() argument
602 if (Buf[0].getKind() == AsmToken::Integer && RegType == Xtensa_Generic) in parseRegister()
615 if (RegType == Xtensa_Generic) in parseRegister()
621 if (RegType == Xtensa_UR) { in parseRegister()
704 XtensaRegisterType RegType, in parseOperand() argument
719 if (parseRegister(Operands, true, RegType, RAType).isSuccess()) in parseOperand()
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| /freebsd/contrib/llvm-project/clang/include/clang/Parse/ |
| H A D | ParseHLSLRootSignature.h | 104 RootSignatureToken::Kind RegType);
115 RootSignatureToken::Kind RegType);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 358 LLT RegType = MRI.getType(Reg); in propagateSPIRVType() local
360 RegType.isPointer() && in propagateSPIRVType()
362 RegType.getAddressSpace()) { in propagateSPIRVType()
365 auto TSC = addressSpaceToStorageClass(RegType.getAddressSpace(), ST); in propagateSPIRVType()
388 LLT RegType = MRI.getType(Reg); in widenScalarType() local
389 if (!RegType.isScalar()) in widenScalarType()
391 unsigned CurrentWidth = RegType.getScalarSizeInBits(); in widenScalarType()
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| H A D | SPIRVInstructionSelector.cpp | 391 LLT RegType = MRI.getType(Reg); in resetVRegsType() local
392 if (RegType.isScalar()) in resetVRegsType()
394 else if (RegType.isPointer()) in resetVRegsType()
396 else if (RegType.isVector()) in resetVRegsType()
3335 SPIRVType *RegType = GR.getSPIRVTypeForVReg(ResourcePtr, I.getMF()); in selectResourceGetPointer() local
3336 if (RegType->getOpcode() == SPIRV::OpTypeImage) { in selectResourceGetPointer()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaHLSL.cpp | 1851 Decl *D, RegisterType RegType, in DiagnoseLocalRegisterBinding() argument
1853 int RegTypeNum = static_cast<int>(RegType); in DiagnoseLocalRegisterBinding()
1865 if (RegType == getRegisterType(RC)) in DiagnoseLocalRegisterBinding()
1881 if (RegType == getRegisterType(AttrResType->getAttrs().ResourceClass)) in DiagnoseLocalRegisterBinding()
1902 if (RegType == RegisterType::CBuffer) in DiagnoseLocalRegisterBinding()
1904 else if (RegType != RegisterType::C) in DiagnoseLocalRegisterBinding()
1909 if (RegType == RegisterType::C) in DiagnoseLocalRegisterBinding()
1952 Decl *D, RegisterType RegType, in DiagnoseHLSLRegisterAttribute() argument
1961 if (!DiagnoseLocalRegisterBinding(S, ArgLoc, D, RegType, SpecifiedSpace)) in DiagnoseHLSLRegisterAttribute()
1965 return ValidateMultipleRegisterAnnotations(S, D, RegType); in DiagnoseHLSLRegisterAttribute()
[all …]
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| /freebsd/contrib/llvm-project/clang/lib/Parse/ |
| H A D | ParseHLSLRootSignature.cpp | 559 TokenKind RegType) { in parseRootDescriptorParams() argument
565 if (tryConsumeExpectedToken(RegType)) { in parseRootDescriptorParams()
634 TokenKind RegType) { in parseDescriptorTableClauseParams() argument
640 if (tryConsumeExpectedToken(RegType)) { in parseDescriptorTableClauseParams()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 6479 string kind1, string kind2, RegisterOperand RegType,
6482 BaseSIMDThreeSameVectorTied<Q, U, {sz, 0b0}, {0b1, opc}, RegType, asm, kind1,
6483 [(set (AccumType RegType:$dst),
6484 (OpNode (AccumType RegType:$Rd),
6485 (InputType RegType:$Rn),
6486 (InputType RegType:$Rm)))]> {
6502 string kind2, RegisterOperand RegType,
6505 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
6506 [(set (AccumType RegType:$dst),
6507 (OpNode (AccumType RegType:$Rd),
[all …]
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| H A D | AArch64FrameLowering.cpp | 3186 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enum
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| H A D | AArch64InstrInfo.td | 1712 string rhs_kind, RegisterOperand RegType,
1715 lhs_kind, rhs_kind, RegType, AccumType,
1717 let Pattern = [(set (AccumType RegType:$dst),
1718 (AccumType (AArch64usdot (AccumType RegType:$Rd),
1722 (InputType RegType:$Rn))))];
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 3405 char RegType = RegTypes[RegNo / 8]; in getRegForInlineAsmConstraint() local
3407 char Tmp[] = {'{', RegType, RegIndex, '}', 0}; in getRegForInlineAsmConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7819 MVT RegType = TLI->getPreferredSwitchConditionType(Context, OldVT); in optimizeSwitchType() local
7820 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType()
7839 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchType()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | Attr.td | 4908 RegisterType RegType;
4915 RegType = RT;
4924 return RegType;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 268 // RegType - Specify the list ValueType of the registers in this register
|