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Searched refs:RegType (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp300 LLT RegType = MRI.getType(Reg); in widenScalarLLTNextPow2() local
301 if (!RegType.isScalar()) in widenScalarLLTNextPow2()
303 unsigned Sz = RegType.getScalarSizeInBits(); in widenScalarLLTNextPow2()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td6123 string kind1, string kind2, RegisterOperand RegType,
6126 BaseSIMDThreeSameVectorTied<Q, U, {sz, 0b0}, {0b1, opc}, RegType, asm, kind1,
6127 [(set (AccumType RegType:$dst),
6128 (OpNode (AccumType RegType:$Rd),
6129 (InputType RegType:$Rn),
6130 (InputType RegType:$Rm)))]> {
6146 string kind2, RegisterOperand RegType,
6149 BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
6150 [(set (AccumType RegType:$dst),
6151 (OpNode (AccumType RegType:$Rd),
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H A DAArch64FrameLowering.cpp2908 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enum
H A DAArch64InstrInfo.td1414 string rhs_kind, RegisterOperand RegType,
1417 lhs_kind, rhs_kind, RegType, AccumType,
1419 let Pattern = [(set (AccumType RegType:$dst),
1420 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd),
1424 (InputType RegType:$Rn))))];
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7427 MVT RegType = TLI->getPreferredSwitchConditionType(Context, OldVT); in optimizeSwitchType() local
7428 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType()
7447 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchType()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3551 char RegType = RegTypes[RegNo / 8]; in getRegForInlineAsmConstraint() local
3553 char Tmp[] = {'{', RegType, RegIndex, '}', 0}; in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td263 // RegType - Specify the list ValueType of the registers in this register