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Searched refs:RegSubRegPair (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp41 using RegSubRegPair = TargetInstrInfo::RegSubRegPair; typedef
46 PrintRegister(RegSubRegPair R, const TargetRegisterInfo &I) in PrintRegister()
50 RegSubRegPair Reg;
80 using SetOfReg = SetVector<RegSubRegPair>;
81 using RegToRegMap = DenseMap<RegSubRegPair, RegSubRegPair>;
92 void processPredicateGPR(const RegSubRegPair &Reg);
96 bool isScalarPred(RegSubRegPair PredReg);
97 RegSubRegPair getPredRegFor(const RegSubRegPair &Reg);
190 RegSubRegPair RD = getRegSubRegPair(MI.getOperand(0)); in collectPredicateGPR()
200 void HexagonGenPredicate::processPredicateGPR(const RegSubRegPair &Reg) { in processPredicateGPR()
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H A DHexagonConstPropagation.cpp80 using RegSubRegPair = TargetInstrInfo::RegSubRegPair; typedef
294 virtual bool evaluate(const RegSubRegPair &R, const LatticeCell &SrcC,
337 bool getCell(const RegSubRegPair &R, const CellMap &Inputs,
343 bool evaluateCMPrr(uint32_t Cmp, const RegSubRegPair &R1,
344 const RegSubRegPair &R2, const CellMap &Inputs,
346 bool evaluateCMPri(uint32_t Cmp, const RegSubRegPair &R1, const APInt &A2,
348 bool evaluateCMPrp(uint32_t Cmp, const RegSubRegPair &R1, uint64_t Props2,
357 bool evaluateCOPY(const RegSubRegPair &R1, const CellMap &Inputs,
361 bool evaluateANDrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
363 bool evaluateANDri(const RegSubRegPair &R1, const APInt &A2,
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H A DHexagonInstrInfo.h538 inline TargetInstrInfo::RegSubRegPair
541 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg()); in getRegSubRegPair()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp100 using RegSubRegPair = TargetInstrInfo::RegSubRegPair; typedef
185 virtual bool getNextRewritableSource(RegSubRegPair &Src,
186 RegSubRegPair &Dst) = 0;
201 bool getNextRewritableSource(RegSubRegPair &Src, in getNextRewritableSource()
202 RegSubRegPair &Dst) override { in getNextRewritableSource()
208 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
211 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
237 bool getNextRewritableSource(RegSubRegPair &Src, in getNextRewritableSource()
238 RegSubRegPair &Dst) override { in getNextRewritableSource()
250 Src = RegSubRegPair(0, 0); in getNextRewritableSource()
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H A DTailDuplicator.cpp357 DenseMap<Register, RegSubRegPair> &LocalVRMap, in processPHI()
358 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &Copies, in processPHI()
366 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
371 Copies.push_back(std::make_pair(NewDef, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
391 DenseMap<Register, RegSubRegPair> &LocalVRMap, in duplicateInstruction()
415 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0))); in duplicateInstruction()
467 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0))); in duplicateInstruction()
921 DenseMap<Register, RegSubRegPair> LocalVRMap; in tailDuplicate()
922 SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos; in tailDuplicate()
981 DenseMap<Register, RegSubRegPair> LocalVRMap; in tailDuplicate()
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H A DMachineSink.cpp122 using RegSubRegPair = TargetInstrInfo::RegSubRegPair; typedef
1753 SmallVector<std::pair<RegSubRegPair, MachineInstr *>> Uses; in aggressivelySinkIntoCycle()
1760 for (std::pair<RegSubRegPair, MachineInstr *> Entry : Uses) { in aggressivelySinkIntoCycle()
1823 RegSubRegPair &UseReg = Entry.first; in aggressivelySinkIntoCycle()
H A DTargetInstrInfo.cpp2015 RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const { in getInsertSubregInputs()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTailDuplicator.h98 using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
104 DenseMap<Register, RegSubRegPair> &LocalVRMap,
105 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &Copies,
109 DenseMap<Register, RegSubRegPair> &LocalVRMap,
125 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &CopyInfos,
H A DTargetInstrInfo.h526 struct RegSubRegPair { struct
530 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0) argument
533 bool operator==(const RegSubRegPair& P) const { argument
536 bool operator!=(const RegSubRegPair& P) const {
544 struct RegSubRegPairAndIdx : RegSubRegPair {
549 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair() function
610 RegSubRegPair &BaseReg,
1473 RegSubRegPair &BaseReg, in getInsertSubregLikeInputs()
2357 template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
2361 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp60 using RegSubRegPair = TargetInstrInfo::RegSubRegPair; typedef in __anon1318784c0111::GCNDPPCombine
65 RegSubRegPair CombOldVGPR,
70 RegSubRegPair CombOldVGPR, bool CombBCZ,
208 RegSubRegPair CombOldVGPR, in createDPPInst()
492 MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR, in createDPPInst()
622 CombOldVGPR = RegSubRegPair( in combineDPPMov()
H A DSIShrinkInstructions.cpp55 TargetInstrInfo::RegSubRegPair getSubRegForIndex(Register Reg, unsigned Sub,
637 TargetInstrInfo::RegSubRegPair
647 return TargetInstrInfo::RegSubRegPair(Reg, Sub); in getSubRegForIndex()
784 TargetInstrInfo::RegSubRegPair X1, Y1; in matchSwap()
H A DSIInstrInfo.h1514 inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, in isOfRegClass()
1526 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) { in getRegSubRegPair()
1528 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg()); in getRegSubRegPair()
1532 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1538 MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
H A DSIInstrInfo.cpp6051 SmallDenseSet<RegSubRegPair> SGPRsUsed; in isOperandLegal()
6053 SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg())); in isOperandLegal()
6060 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg()); in isOperandLegal()
9758 TargetInstrInfo::RegSubRegPair getRegOrUndef(const MachineOperand &RegOpnd) { in getRegOrUndef()
9760 return RegOpnd.isUndef() ? TargetInstrInfo::RegSubRegPair() : in getRegOrUndef()
9764 TargetInstrInfo::RegSubRegPair
9772 return TargetInstrInfo::RegSubRegPair(); in getRegSequenceSubReg()
9778 TargetInstrInfo::RegSubRegPair &RSR) { in followSubRegDef()
9802 MachineInstr *llvm::getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, in getVRegSubRegDef()
H A DSIFoldOperands.cpp1820 DenseMap<TargetInstrInfo::RegSubRegPair, Register> VGPRCopies; in foldCopyToAGPRRegSequence()
1895 TargetInstrInfo::RegSubRegPair Src = getRegSubRegPair(*Def); in foldCopyToAGPRRegSequence()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h96 RegSubRegPair &BaseReg,
H A DARMBaseInstrInfo.cpp5350 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, in getInsertSubregLikeInputs()