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Searched refs:RegSize (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp153 static bool splitBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc, T &Imm2Enc) { in splitBitmaskImm() argument
155 if (AArch64_AM::isLogicalImmediate(UImm, RegSize)) in splitBitmaskImm()
160 AArch64_IMM::expandMOVImm(UImm, RegSize, Insn); in splitBitmaskImm()
182 if (!AArch64_AM::isLogicalImmediate(NewImm2, RegSize)) in splitBitmaskImm()
185 Imm1Enc = AArch64_AM::encodeLogicalImmediate(NewImm1, RegSize); in splitBitmaskImm()
186 Imm2Enc = AArch64_AM::encodeLogicalImmediate(NewImm2, RegSize); in splitBitmaskImm()
205 [Opc](T Imm, unsigned RegSize, T &Imm0, in visitAND()
207 if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1)) in visitAND()
332 static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) { in splitAddSubImm() argument
341 AArch64_IMM::expandMOVImm(Imm, RegSize, Insn); in splitAddSubImm()
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H A DAArch64FastISel.cpp1671 unsigned RegSize; in emitLogicalOp_ri() local
1682 RegSize = 32; in emitLogicalOp_ri()
1688 RegSize = 64; in emitLogicalOp_ri()
1692 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1697 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4116 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4163 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4219 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4267 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4335 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
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H A DAArch64FrameLowering.cpp3709 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
3712 SVECSStackSize += RegSize; in determineCalleeSaves()
3714 CSStackSize += RegSize; in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DInfoByHwMode.cpp119 RegSize = R->getValueAsInt("RegSize"); in RegSizeInfo()
125 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
126 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
130 return RegSize <= I.RegSize && SpillAlignment && in isSubClassOf()
135 OS << "[R=" << RegSize << ",S=" << SpillSize << ",A=" << SpillAlignment in writeToStream()
H A DInfoByHwMode.h182 unsigned RegSize; member
190 return std::tie(RegSize, SpillSize, SpillAlignment) ==
191 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFrameLowering.cpp127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
128 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
H A DMipsCallLowering.cpp413 unsigned RegSize = 4; in lowerFormalArguments() local
415 VaArgOffset = alignTo(CCInfo.getStackSize(), RegSize); in lowerFormalArguments()
419 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
423 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
426 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
428 LLT RegTy = LLT::scalar(RegSize * 8); in lowerFormalArguments()
431 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
437 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize)); in lowerFormalArguments()
H A DMipsSEFrameLowering.cpp78 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80 unsigned MFLoOpc, unsigned RegSize);
198 unsigned RegSize) { in expandLoadACC() argument
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC() argument
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp139 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
145 SmallBitVector Coverage(RegSize, false); in addMachineReg()
156 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
180 if (CurPos < RegSize) in addMachineReg()
182 -1, RegSize - CurPos, "no DWARF register encoding")); in addMachineReg()
292 unsigned RegSize = 0; in addMachineRegExpression() local
294 RegSize += Reg.SubRegSize; in addMachineRegExpression()
298 if (RegSize > FragmentInfo->SizeInBits) in addMachineRegExpression()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp184 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY() local
185 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16)) in INITIALIZE_PASS_DEPENDENCY()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
216 (RegSize != 64 && in processLogicalImmediate()
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
221 unsigned Size = RegSize; in processLogicalImmediate()
214 processLogicalImmediate(uint64_t Imm,unsigned RegSize,uint64_t & Encoding) processLogicalImmediate() argument
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DX86.h241 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
247 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
787 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
793 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
798 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, in validateGlobalRegisterVariable()
H A DAArch64.h206 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
H A DAArch64.cpp232 StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const { in validateGlobalRegisterVariable() argument
234 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
237 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DAArch64.cpp583 int RegSize = IsIndirect ? 8 : TySize.getQuantity(); in EmitAAPCSVAArg() local
589 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
595 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
636 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
H A DPPC.cpp510 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
512 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
516 RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1050 uint32_t RegSize = 0; in runMCDesc() local
1052 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1056 << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1286 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h243 unsigned RegSize, SpillSize, SpillAlignment; member
298 return TypeSize::getFixed(getRegClassInfo(RC).RegSize); in getRegSizeInBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
430 CSStackSize += RegSize; in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1036 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
1038 explicit operator bool() const { return RegSize; } in operator bool()
1040 unsigned RegSize = 0; member
1087 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
1089 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
1091 if (And.RegSize == 64) { in convertToThreeAddress()
H A DSystemZFrameLowering.cpp1036 unsigned RegSize = getPointerSize(); in assignCalleeSavedSpillSlots() local
1040 : MFFrame.CreateFixedSpillStackObject(RegSize, Offset); in assignCalleeSavedSpillSlots()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp509 unsigned RegSize = RegTy.getSizeInBits(); in extractParts() local
511 unsigned NumParts = RegSize / MainSize; in extractParts()
512 unsigned LeftoverSize = RegSize - NumParts * MainSize; in extractParts()
587 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; in extractParts()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGRecordLayoutBuilder.cpp505 CharUnits RegSize = in accumulateBitFields() local
598 } else if (AccessSize > RegSize) in accumulateBitFields()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp560 int RegSize; in sizeOfSPAdjustment() local
563 RegSize = 8; in sizeOfSPAdjustment()
567 RegSize = 4; in sizeOfSPAdjustment()
580 count += RegSize; in sizeOfSPAdjustment()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DTargetInfo.h1191 unsigned RegSize, in validateGlobalRegisterVariable() argument

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