| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 159 static bool splitBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc, T &Imm2Enc) { in splitBitmaskImm() argument
161 if (AArch64_AM::isLogicalImmediate(UImm, RegSize)) in splitBitmaskImm()
166 AArch64_IMM::expandMOVImm(UImm, RegSize, Insn); in splitBitmaskImm()
188 if (!AArch64_AM::isLogicalImmediate(NewImm2, RegSize)) in splitBitmaskImm()
191 Imm1Enc = AArch64_AM::encodeLogicalImmediate(NewImm1, RegSize); in splitBitmaskImm()
192 Imm2Enc = AArch64_AM::encodeLogicalImmediate(NewImm2, RegSize); in splitBitmaskImm()
211 [Opc](T Imm, unsigned RegSize, T &Imm0, in visitAND()
213 if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1)) in visitAND()
361 static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) { in splitAddSubImm() argument
370 AArch64_IMM::expandMOVImm(Imm, RegSize, Insn); in splitAddSubImm()
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| H A D | AArch64FastISel.cpp | 1668 unsigned RegSize; in emitLogicalOp_ri() local
1679 RegSize = 32; in emitLogicalOp_ri()
1685 RegSize = 64; in emitLogicalOp_ri()
1689 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1694 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4117 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4164 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4221 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4269 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4338 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | InfoByHwMode.cpp | 121 RegSize = R->getValueAsInt("RegSize"); in RegSizeInfo()
127 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
128 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
132 return RegSize <= I.RegSize && SpillAlignment && in isSubClassOf()
137 OS << "[R=" << RegSize << ",S=" << SpillSize << ",A=" << SpillAlignment in writeToStream()
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| H A D | InfoByHwMode.h | 183 unsigned RegSize; member
191 return std::tie(RegSize, SpillSize, SpillAlignment) ==
192 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFrameLowering.cpp | 121 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
122 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
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| H A D | MipsCallLowering.cpp | 411 unsigned RegSize = 4; in lowerFormalArguments() local
413 VaArgOffset = alignTo(CCInfo.getStackSize(), RegSize); in lowerFormalArguments()
417 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
421 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
424 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
426 LLT RegTy = LLT::scalar(RegSize * 8); in lowerFormalArguments()
429 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
435 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize)); in lowerFormalArguments()
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| H A D | MipsSEFrameLowering.cpp | 76 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
78 unsigned MFLoOpc, unsigned RegSize);
196 unsigned RegSize) { in expandLoadACC() argument
204 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
215 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
221 unsigned RegSize) { in expandStoreACC() argument
229 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
239 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 145 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
151 SmallBitVector Coverage(RegSize, false); in addMachineReg()
162 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
186 if (CurPos < RegSize) in addMachineReg()
188 -1, RegSize - CurPos, "no DWARF register encoding")); in addMachineReg()
298 unsigned RegSize = 0; in addMachineRegExpression() local
300 RegSize += Reg.SubRegSize; in addMachineRegExpression()
304 if (RegSize > FragmentInfo->SizeInBits) in addMachineRegExpression()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TileConfig.cpp | 243 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in runOnMachineFunction() local
244 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16)) in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && in processLogicalImmediate()
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
221 unsigned Size = RegSize; in processLogicalImmediate()
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| /freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | X86.h | 253 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
259 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
818 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
824 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
829 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, in validateGlobalRegisterVariable()
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| H A D | RISCV.cpp | 625 StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const { in validateGlobalRegisterVariable() argument
630 HasSizeMismatch = RegSize != XLen; in validateGlobalRegisterVariable()
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| H A D | RISCV.h | 139 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
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| H A D | AArch64.cpp | 234 StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const { in validateGlobalRegisterVariable() argument
236 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
240 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
242 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
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| H A D | AArch64.h | 254 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 666 unsigned RegSize = IsRV64 ? 8 : 4; in getStackAdjBase() local
667 return alignTo(NumRegs * RegSize, 16); in getStackAdjBase()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | AArch64.cpp | 916 int RegSize = IsIndirect ? 8 : TySize.getQuantity(); in EmitAAPCSVAArg() local
922 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
928 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
969 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
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| H A D | PPC.cpp | 514 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
516 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
520 RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1087 uint32_t RegSize = 0; in runMCDesc() local
1089 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1093 << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1325 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
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| /freebsd/sys/contrib/dev/acpica/common/ |
| H A D | dmtbinfo1.c | 1376 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (RegSize), "MBM Register Size", 0},
1437 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (RegSize), "CMRD Register Size", 0},
1458 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (RegSize), "IBRD Register Size", 0},
1503 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (RegSize), "CARD Register Size", 0},
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 242 unsigned RegSize, SpillSize, SpillAlignment; member
297 return TypeSize::getFixed(getRegClassInfo(RC).RegSize); in getRegSizeInBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
430 CSStackSize += RegSize; in determineCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 519 unsigned RegSize = 4; in LowerFormalArguments() local
539 VarArgsSaveSize = RegSize * (ArgRegsNum - Idx); in LowerFormalArguments()
544 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in LowerFormalArguments()
549 for (unsigned I = Idx; I < ArgRegsNum; ++I, VaArgOffset += RegSize) { in LowerFormalArguments()
554 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1067 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
1069 explicit operator bool() const { return RegSize; } in operator bool()
1071 unsigned RegSize = 0; member
1118 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
1120 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
1122 if (And.RegSize == 64) { in convertToThreeAddress()
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| /freebsd/sys/contrib/dev/acpica/include/ |
| H A D | actbl2.h | 771 UINT32 RegSize; member
818 UINT32 RegSize; member
836 UINT32 RegSize; member
870 UINT32 RegSize; member
|