| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 67 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
252 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet() argument
255 if (RegSet.count(*AI)) in isRegInSet()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 278 using RegSet = SparseSet<IndexMaskPair>; variable
279 RegSet Regs;
301 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
324 RegSet::iterator I = Regs.find(SparseIndex); in erase()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 72 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
356 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) in IsRegInSet() argument
361 if (RegSet.count(*AI)) in IsRegInSet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 131 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
440 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet() argument
443 if (RegSet.test(*AI)) in isRegInSet()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 42 const uint8_t *const RegSet; variable
80 return (RegSet[Byte] & (1 << InByte)) != 0; in contains()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 205 void updateLiveness(const std::set<Register> &RegSet, bool Recalc,
536 void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet, in updateLiveness() argument
540 for (Register R : RegSet) { in updateLiveness()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 257 SmallSet<Register, 4> RegSet; in AntiDepEdges() local
260 if (RegSet.insert(Pred.getReg()).second) in AntiDepEdges()
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| H A D | RegAllocPBQP.cpp | 146 using RegSet = std::set<Register>; typedef in __anonda0ac5d00111::RegAllocPBQP
150 RegSet VRegsToAlloc, EmptyIntervalVRegs;
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| H A D | MachineVerifier.cpp | 142 using RegSet = DenseSet<Register>; typedef
151 RegSet regsLive;
175 RegSet regsKilled;
179 RegSet regsLiveOut;
183 RegSet vregsPassed;
187 RegSet vregsRequired;
205 bool addRequired(const RegSet &RS) { in addRequired()
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| H A D | MachinePipeliner.cpp | 1680 const auto InsertReg = [this, &CurSetPressure](RegSetTy &RegSet, in computeMaxSetPressure()
1685 bool Inserted = RegSet.insert(Reg).second; in computeMaxSetPressure()
1694 const auto EraseReg = [this, &CurSetPressure](RegSetTy &RegSet, in computeMaxSetPressure() argument
1700 if (!RegSet.contains(Reg)) in computeMaxSetPressure()
1704 RegSet.erase(Reg); in computeMaxSetPressure()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 827 const std::set<Register> &RegSet) { in getNextOrderedReg() argument
829 [&](Register Reg) { return RegSet.count(Reg); }); in getNextOrderedReg()
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