Home
last modified time | relevance | path

Searched refs:RegPos (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveIntervalUnion.cpp35 LiveRange::const_iterator RegPos = Range.begin(); in unify()
37 SegmentIter SegPos = Segments.find(RegPos->start); in unify()
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
41 if (++RegPos == RegEnd) in unify()
43 SegPos.advanceTo(RegPos->start); in unify()
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify()
52 SegPos.insert(RegPos->start, RegPos in unify()
36 LiveRange::const_iterator RegPos = Range.begin(); unify() local
64 LiveRange::const_iterator RegPos = Range.begin(); extract() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMemAbsolute.cpp122 unsigned BaseRegPos, ImmPos, RegPos; in runOnMachineFunction() local
125 RegPos = IsLoad ? 0 : 2; in runOnMachineFunction()
147 const MachineOperand &MO0 = NextMI->getOperand(RegPos); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp1424 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1426 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
1487 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local
1489 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()