| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMoveMerger.cpp | 35 bool isCandidateToMergeMVA01S(const DestSourcePair &RegPair);
36 bool isCandidateToMergeMVSA01(const DestSourcePair &RegPair);
47 const DestSourcePair &RegPair);
102 bool RISCVMoveMerge::isCandidateToMergeMVA01S(const DestSourcePair &RegPair) { in isCandidateToMergeMVA01S() argument
103 Register Destination = RegPair.Destination->getReg(); in isCandidateToMergeMVA01S()
104 Register Source = RegPair.Source->getReg(); in isCandidateToMergeMVA01S()
113 bool RISCVMoveMerge::isCandidateToMergeMVSA01(const DestSourcePair &RegPair) { in isCandidateToMergeMVSA01() argument
114 Register Destination = RegPair.Destination->getReg(); in isCandidateToMergeMVSA01()
115 Register Source = RegPair.Source->getReg(); in isCandidateToMergeMVSA01()
179 const DestSourcePair &RegPair) { in findMatchingInst() argument
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| H A D | RISCVISelDAGToDAG.cpp | 1826 SDValue RegPair; in Select() local
1829 RegPair = CurDAG->getRegister(RISCV::X0_Pair, MVT::Untyped); in Select()
1836 RegPair = SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, in Select()
1842 {RegPair, Base, Offset, Chain}); in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1361 auto GetRegPair = [this, r](RegPairVals RegPair) { in processInstruction() argument
1362 const std::string R1 = r + utostr(RegPair.first); in processInstruction()
1363 const std::string R2 = r + utostr(RegPair.second); in processInstruction()
1367 auto GetScalarRegs = [RI, GetRegPair](MCRegister RegPair) { in processInstruction() argument
1368 const unsigned Lower = RI->getEncodingValue(RegPair); in processInstruction()
1374 const RegPairVals RegPair = in processInstruction() local
1377 return GetRegPair(RegPair); in processInstruction()
1470 const std::pair<MCRegister, MCRegister> RegPair = in processInstruction() local
1472 MO.setReg(RegPair.first); in processInstruction()
1473 Inst.addOperand(MCOperand::createReg(RegPair.second)); in processInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 1109 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI() local
1110 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1115 MRI.clearKillFlags(RegPair.Reg); in insertPHI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 480 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2356 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); in DecodeMovePOperands() local
2357 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == in DecodeMovePOperands()
2379 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, in DecodeMovePRegPair() argument
2382 switch (RegPair) { in DecodeMovePRegPair()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 222 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); in encodeInstruction() local
223 Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7); in encodeInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 555 for (auto const &RegPair : RegsToPass) in LowerCall() local
556 resetRegMaskBit(TRI, RegMask, RegPair.first); in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 2538 for (auto const &RegPair : RegsToPass) in LowerCall() local
2539 for (MCPhysReg SubReg : TRI->subregs_inclusive(RegPair.first)) in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 4085 SDNode *RegPair = in Select() local
4087 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2262 bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) || in processInstruction() local
2270 if (!RegPair) in processInstruction()
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