Searched refs:RegOpnd (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 570 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in EncodeZPR4StridedRegisterClass()
571 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR4StridedRegisterClass()
579 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in EncodeMatrixTileListRegisterClass()
580 return RegOpnd - AArch64::PN8; in EncodeMatrixTileListRegisterClass()
586 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in encodeMatrixIndexGPR32()
587 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in encodeMatrixIndexGPR32() local
596 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in getImm8OptLsl()
597 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in getImm8OptLsl()
616 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in getSVEIncDecImm()
617 return RegOpnd in getSVEIncDecImm()
541 auto RegOpnd = MI.getOperand(OpIdx).getReg(); EncodeRegAsMultipleOf() local
550 auto RegOpnd = MI.getOperand(OpIdx).getReg(); EncodePPR_p8to15() local
557 auto RegOpnd = MI.getOperand(OpIdx).getReg(); EncodeZPR2StridedRegisterClass() local
567 auto RegOpnd = MI.getOperand(OpIdx).getReg(); EncodeZPR4StridedRegisterClass() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 818 SDNode *RegOpnd; in trySelect() local
826 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); in trySelect()
828 RegOpnd = in trySelect()
837 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in trySelect()
838 SDValue(RegOpnd, 0), ImmOpnd); in trySelect()
841 ReplaceNode(Node, RegOpnd); in trySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 7708 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpAdd() local
7709 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpAdd()
7710 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpAdd()
7721 getTargetStreamer().emitDirectiveCpAdd(RegOpnd.getGPR32Reg()); in parseDirectiveCpAdd()
7741 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpLoad() local
7742 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpLoad()
7743 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpLoad()
7753 getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg()); in parseDirectiveCpLoad()
7770 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpLocal() local
7771 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpLocal()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 9291 TargetInstrInfo::RegSubRegPair getRegOrUndef(const MachineOperand &RegOpnd) { in getRegOrUndef() argument
9292 assert(RegOpnd.isReg()); in getRegOrUndef()
9293 return RegOpnd.isUndef() ? TargetInstrInfo::RegSubRegPair() : in getRegOrUndef()
9294 getRegSubRegPair(RegOpnd); in getRegOrUndef()
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