Searched refs:RegOpnd (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 583 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in EncodeRegMul_MinMax() local
584 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeRegMul_MinMax()
595 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in EncodeZK() local
596 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZK()
599 if (RegOpnd > AArch64::Z27) in EncodeZK()
602 assert((RegOpnd > AArch64::Z19 && RegOpnd < AArch64::Z24) && in EncodeZK()
612 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in EncodePNR_p8to15() local
613 return RegOpnd - AArch64::PN8; in EncodePNR_p8to15()
619 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in EncodeZPR2StridedRegisterClass() local
620 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR2StridedRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 764 SDNode *RegOpnd; in trySelect() local
772 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); in trySelect()
774 RegOpnd = in trySelect()
783 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in trySelect()
784 SDValue(RegOpnd, 0), ImmOpnd); in trySelect()
787 ReplaceNode(Node, RegOpnd); in trySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 7702 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpAdd() local
7703 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpAdd()
7704 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpAdd()
7715 getTargetStreamer().emitDirectiveCpAdd(RegOpnd.getGPR32Reg()); in parseDirectiveCpAdd()
7735 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpLoad() local
7736 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpLoad()
7737 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpLoad()
7747 getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg()); in parseDirectiveCpLoad()
7764 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpLocal() local
7765 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpLocal()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 9758 TargetInstrInfo::RegSubRegPair getRegOrUndef(const MachineOperand &RegOpnd) { in getRegOrUndef() argument
9759 assert(RegOpnd.isReg()); in getRegOrUndef()
9760 return RegOpnd.isUndef() ? TargetInstrInfo::RegSubRegPair() : in getRegOrUndef()
9761 getRegSubRegPair(RegOpnd); in getRegOrUndef()
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