Searched refs:RegOp0 (Results 1 – 3 of 3) sorted by relevance
119 MCRegister RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch() local122 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch()141 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
1171 MachineOperand RegOp0 = getLdStRegOp(*RtMI); in mergePairedInsns() local1173 MachineOperand &PairedRegOp = RtMI == &*Paired ? RegOp0 : RegOp1; in mergePairedInsns()1175 if (RegOp0.isUse()) { in mergePairedInsns()1208 MIB.add(RegOp0) in mergePairedInsns()
5479 Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in EmitInstrWithCustomInserter() local5480 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0) in EmitInstrWithCustomInserter()5482 Src0.setReg(RegOp0); in EmitInstrWithCustomInserter()