| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.cpp | 90 lookupFoldTableImpl(ArrayRef<X86FoldTableEntry> Table, unsigned RegOp) { in lookupFoldTableImpl() argument
117 const X86FoldTableEntry *Data = llvm::lower_bound(Table, RegOp); in lookupFoldTableImpl()
118 if (Data != Table.end() && Data->KeyOp == RegOp && in lookupFoldTableImpl()
124 const X86FoldTableEntry *llvm::lookupTwoAddrFoldTable(unsigned RegOp) { in lookupTwoAddrFoldTable() argument
125 return lookupFoldTableImpl(Table2Addr, RegOp); in lookupTwoAddrFoldTable()
128 const X86FoldTableEntry *llvm::lookupFoldTable(unsigned RegOp, unsigned OpNum) { in lookupFoldTable() argument
143 return lookupFoldTableImpl(FoldTable, RegOp); in lookupFoldTable()
146 const X86FoldTableEntry *llvm::lookupBroadcastFoldTable(unsigned RegOp, in lookupBroadcastFoldTable() argument
160 return lookupFoldTableImpl(FoldTable, RegOp); in lookupBroadcastFoldTable()
250 unsigned RegOp = Reg2Bcst.KeyOp; in X86BroadcastFoldTable() local
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| H A D | X86InstrFoldTables.h | 41 const X86FoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
45 const X86FoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
49 const X86FoldTableEntry *lookupBroadcastFoldTable(unsigned RegOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 210 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
211 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
215 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
235 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
244 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
249 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
253 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
259 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
269 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
278 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 577 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
578 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
579 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
580 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
581 getUndefRegState(RegOp.isUndef()) | in getRegState()
582 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
583 getDebugRegState(RegOp.isDebug()) | in getRegState()
584 getRenamableRegState(RegOp.getReg().isPhysical() && in getRegState()
585 RegOp.isRenamable()); in getRegState()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFInstPrinter.cpp | 50 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
54 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
55 O << getRegisterName(RegOp.getReg()); in printMemOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAsmPrinter.cpp | 128 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
129 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
131 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCCodeEmitter.cpp | 144 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
147 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
151 switch (RegOp.getReg().id()) { in encodeMemri()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1832 MachineOperand &RegOp = RegSeq->getOperand(I); in foldCopyToAGPRRegSequence() local
1835 if (RegOp.getSubReg()) { in foldCopyToAGPRRegSequence()
1837 NewDefs.emplace_back(&RegOp, SubRegIdx); in foldCopyToAGPRRegSequence()
1841 MachineOperand *Lookup = lookUpCopyChain(*TII, *MRI, RegOp.getReg()); in foldCopyToAGPRRegSequence()
1843 Lookup = &RegOp; in foldCopyToAGPRRegSequence()
1859 : MRI->getRegClass(RegOp.getReg()); in foldCopyToAGPRRegSequence()
1871 NewDefs.emplace_back(&RegOp, SubRegIdx); in foldCopyToAGPRRegSequence()
1875 NewDefs.emplace_back(&RegOp, SubRegIdx); in foldCopyToAGPRRegSequence()
2220 const MachineOperand *RegOp = nullptr; in isOMod() local
2226 RegOp = Src1; in isOMod()
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| H A D | SIInstrInfo.cpp | 1241 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1242 RegOp.setImplicit(false); in insertVectorSelect()
1245 .add(RegOp); in insertVectorSelect()
1255 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1256 RegOp.setImplicit(false); in insertVectorSelect()
1259 .add(RegOp); in insertVectorSelect()
2745 MachineOperand &RegOp, in swapRegAndNonRegOperand() argument
2747 Register Reg = RegOp.getReg(); in swapRegAndNonRegOperand()
2748 unsigned SubReg = RegOp.getSubReg(); in swapRegAndNonRegOperand()
2749 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 544 unsigned RegOp = OpNum; in PrintAsmOperand() local
550 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
553 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
556 RegOp = OpNum + 1; in PrintAsmOperand()
558 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
560 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1096 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrix() local
1097 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrix()
1099 printRegName(O, RegOp.getReg()); in printMatrix()
1127 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTileVector() local
1128 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTileVector()
1129 StringRef RegName = getRegisterName(RegOp.getReg()); in printMatrixTileVector()
1140 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTile() local
1141 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTile()
1142 printRegName(O, RegOp.getReg()); in printMatrixTile()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 90 struct RegOp { struct
101 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1708 unsigned RegOp = CurOp++; in encodeInstruction() local
1711 emitMemModRMByte(MI, MemOp, getX86RegNum(MI.getOperand(RegOp)), TSFlags, in encodeInstruction()
1830 unsigned RegOp = CurOp++; in encodeInstruction() local
1837 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), in encodeInstruction()
1843 unsigned RegOp = CurOp++; in encodeInstruction() local
1847 emitRegModRMByte(MI.getOperand(RegOp), 0, CB); in encodeInstruction()
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| H A D | X86EncodingOptimization.cpp | 365 unsigned RegOp = IsStore ? 0 : 5; in optimizeMOV() local
368 MCRegister Reg = MI.getOperand(RegOp).getReg(); in optimizeMOV()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 359 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs() local
360 if (!RegOp.isVirtual()) in collectUnprimedAccPHIs()
362 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs()
403 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs() local
404 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
| H A D | XtensaAsmParser.cpp | 123 struct RegOp { struct
134 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 49 struct RegOp { struct
84 struct RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 588 MachineOperand &RegOp = PI.getOperand(i); in preprocessPhiNodes() local
589 if (RegOp.getSubReg() == 0) in preprocessPhiNodes()
599 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
600 RegOp.getSubReg()); in preprocessPhiNodes()
602 RegOp.setReg(NewReg); in preprocessPhiNodes()
603 RegOp.setSubReg(0); in preprocessPhiNodes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 119 struct RegOp { struct
136 struct RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 416 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; in PrintAsmOperand() local
417 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
419 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 115 struct RegOp { struct in __anonde0c959e0111::SystemZOperand
145 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 171 struct RegOp { struct in __anon944a62760211::VEOperand
201 struct RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 156 struct RegOp { struct
187 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 237 struct RegOp { struct in __anonebada3920211::SparcOperand
254 struct RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 215 struct RegOp { struct in __anon571544da0111::LoongArchOperand
226 struct RegOp Reg;
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