| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.cpp | 90 lookupFoldTableImpl(ArrayRef<X86FoldTableEntry> Table, unsigned RegOp) { in lookupFoldTableImpl() argument
117 const X86FoldTableEntry *Data = llvm::lower_bound(Table, RegOp); in lookupFoldTableImpl()
118 if (Data != Table.end() && Data->KeyOp == RegOp && in lookupFoldTableImpl()
124 const X86FoldTableEntry *llvm::lookupTwoAddrFoldTable(unsigned RegOp) { in lookupTwoAddrFoldTable() argument
125 return lookupFoldTableImpl(Table2Addr, RegOp); in lookupTwoAddrFoldTable()
128 const X86FoldTableEntry *llvm::lookupFoldTable(unsigned RegOp, unsigned OpNum) { in lookupFoldTable() argument
143 return lookupFoldTableImpl(FoldTable, RegOp); in lookupFoldTable()
146 const X86FoldTableEntry *llvm::lookupBroadcastFoldTable(unsigned RegOp, in lookupBroadcastFoldTable() argument
160 return lookupFoldTableImpl(FoldTable, RegOp); in lookupBroadcastFoldTable()
250 unsigned RegOp = Reg2Bcst.KeyOp; in X86BroadcastFoldTable() local
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| H A D | X86InstrFoldTables.h | 41 const X86FoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
45 const X86FoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
49 const X86FoldTableEntry *lookupBroadcastFoldTable(unsigned RegOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 214 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
215 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
249 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
255 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
265 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
276 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
285 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVDuplicatesTracker.cpp | 65 MachineOperand *RegOp = &VRegDef->getOperand(0); in buildDepsGraph() local
67 Reg2Entry.count(RegOp)); in buildDepsGraph()
68 if (Reg2Entry.count(RegOp)) in buildDepsGraph()
69 E->addDep(Reg2Entry[RegOp]); in buildDepsGraph()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 575 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
576 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
577 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
578 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
579 getUndefRegState(RegOp.isUndef()) | in getRegState()
580 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
581 getDebugRegState(RegOp.isDebug()) | in getRegState()
582 getRenamableRegState(RegOp.getReg().isPhysical() && in getRegState()
583 RegOp.isRenamable()); in getRegState()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFInstPrinter.cpp | 72 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand()
76 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
77 O << getRegisterName(RegOp.getReg()); in printMemOperand()
69 const MCOperand &RegOp = MI->getOperand(OpNo); printMemOperand() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAsmPrinter.cpp | 130 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
131 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
133 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCCodeEmitter.cpp | 140 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
143 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
147 switch (RegOp.getReg()) { in encodeMemri()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 544 unsigned RegOp = OpNum; in PrintAsmOperand() local
550 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
553 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
556 RegOp = OpNum + 1; in PrintAsmOperand()
558 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
560 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1677 const MachineOperand *RegOp = nullptr; in isOMod() local
1683 RegOp = Src1; in isOMod()
1686 RegOp = Src0; in isOMod()
1698 return std::pair(RegOp, OMod); in isOMod()
1736 const MachineOperand *RegOp; in tryFoldOMod() local
1738 std::tie(RegOp, OMod) = isOMod(MI); in tryFoldOMod()
1739 if (OMod == SIOutMods::NONE || !RegOp->isReg() || in tryFoldOMod()
1740 RegOp->getSubReg() != AMDGPU::NoSubRegister || in tryFoldOMod()
1741 !MRI->hasOneNonDBGUser(RegOp->getReg())) in tryFoldOMod()
1744 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod()
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 1832 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfBlock() local
1833 ArrayRef<MachineOperand> Cond(RegOp); in createIfBlock()
2289 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
2290 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
2292 LLVM_DEBUG(RegOp.print(dbgs(), TRI)); in createIfRegion()
2345 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
2346 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
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| H A D | SIInstrInfo.cpp | 1280 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1281 RegOp.setImplicit(false); in insertVectorSelect()
1284 .add(RegOp); in insertVectorSelect()
1294 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1295 RegOp.setImplicit(false); in insertVectorSelect()
1298 .add(RegOp); in insertVectorSelect()
2740 MachineOperand &RegOp, in swapRegAndNonRegOperand() argument
2742 Register Reg = RegOp.getReg(); in swapRegAndNonRegOperand()
2743 unsigned SubReg = RegOp.getSubReg(); in swapRegAndNonRegOperand()
2744 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1081 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrix()
1082 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrix()
1084 printRegName(O, RegOp.getReg()); in printMatrix()
1112 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTile()
1113 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTile()
1114 StringRef RegName = getRegisterName(RegOp.getReg());
1125 const MCOperand &RegOp = MI->getOperand(OpNum);
1126 assert(RegOp.isReg() && "Unexpected operand type!"); in printOperand()
1127 printRegName(O, RegOp.getReg()); in printOperand()
1066 const MCOperand &RegOp = MI->getOperand(OpNum); printMatrix() local
1097 const MCOperand &RegOp = MI->getOperand(OpNum); printMatrixTileVector() local
1110 const MCOperand &RegOp = MI->getOperand(OpNum); printMatrixTile() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 88 struct RegOp { struct
99 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1699 unsigned RegOp = CurOp++; in encodeInstruction() local
1702 emitMemModRMByte(MI, MemOp, getX86RegNum(MI.getOperand(RegOp)), TSFlags, in encodeInstruction()
1821 unsigned RegOp = CurOp++; in encodeInstruction() local
1828 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), in encodeInstruction()
1834 unsigned RegOp = CurOp++; in encodeInstruction() local
1838 emitRegModRMByte(MI.getOperand(RegOp), 0, CB); in encodeInstruction()
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| H A D | X86EncodingOptimization.cpp | 364 unsigned RegOp = IsStore ? 0 : 5; in optimizeMOV() local
367 unsigned Reg = MI.getOperand(RegOp).getReg(); in optimizeMOV()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
| H A D | XtensaAsmParser.cpp | 111 struct RegOp { struct
122 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 363 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs() local
364 if (!RegOp.isVirtual()) in collectUnprimedAccPHIs()
366 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs()
407 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs() local
408 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 49 struct RegOp { struct
84 struct RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 449 MachineOperand &RegOp = PI.getOperand(i); in preprocessPhiNodes() local
450 if (RegOp.getSubReg() == 0) in preprocessPhiNodes()
460 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
461 RegOp.getSubReg()); in preprocessPhiNodes()
463 RegOp.setReg(NewReg); in preprocessPhiNodes()
464 RegOp.setSubReg(0); in preprocessPhiNodes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 120 struct RegOp { struct
137 struct RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 413 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; in PrintAsmOperand() local
414 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
416 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 110 struct RegOp { struct in __anonde0c959e0111::SystemZOperand
140 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 156 struct RegOp { struct
187 RegOp Reg;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 233 struct RegOp { struct in __anonebada3920211::SparcOperand
250 struct RegOp Reg;
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