| /freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | Sparc.cpp | 114 unsigned &RegOffset) const;
228 unsigned &RegOffset) const { in classifyType()
237 bool NeedPadding = (Alignment > 64) && (RegOffset % 2 != 0); in classifyType()
242 RegOffset += 1; in classifyType()
254 RegOffset += 1; in classifyType()
260 RegOffset += 1; in classifyType()
266 RegOffset += Size / 64; in classifyType()
273 RegOffset += 1; in classifyType()
282 RegOffset += Size / 64; in classifyType()
293 RegOffset += CB.Size / 64; in classifyType()
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| H A D | SystemZ.cpp | 366 llvm::Value *RegOffset = in EmitVAArg() local
373 CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, RegOffset, "raw_reg_addr"), in EmitVAArg()
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| H A D | PPC.cpp | 515 llvm::Value *RegOffset = in EmitVAArg() local
518 CGF.Int8Ty, RegAddr.emitRawPointer(CGF), RegOffset), in EmitVAArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1762 for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e; in buildSpillLoadStore() local
1763 ++i, RegOffset += EltSize) { in buildSpillLoadStore()
1790 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore()
1817 for (int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS, in buildSpillLoadStore()
1818 LaneE = RegOffset / 4; in buildSpillLoadStore()
1851 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore()
1885 MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(RegOffset); in buildSpillLoadStore()
1888 commonAlignment(Alignment, RegOffset)); in buildSpillLoadStore()
1916 MIB.addImm(Offset + RegOffset); in buildSpillLoadStore()
1990 for (unsigned RegOffset = 1; RegOffset < 32; ++RegOffset) in addImplicitUsesForBlockCSRLoad() local
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| /freebsd/sys/dev/mps/ |
| H A D | mps_ioctl.h | 335 uint32_t RegOffset; member
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| H A D | mps_user.c | 2080 data->RegData = mps_regread(sc, data->RegOffset); in mps_user_reg_access()
2084 mps_regwrite(sc, data->RegOffset, data->RegData); in mps_user_reg_access()
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| /freebsd/sys/dev/mpr/ |
| H A D | mpr_ioctl.h | 334 uint32_t RegOffset; member
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| H A D | mpr_user.c | 2192 data->RegData = mpr_regread(sc, data->RegOffset); in mpr_user_reg_access()
2196 mpr_regwrite(sc, data->RegOffset, data->RegData); in mpr_user_reg_access()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 132 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); in addMachineReg() local
135 setSubRegisterPiece(Size, RegOffset); in addMachineReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 1309 int RegOffset = Offset->second; in generateCompactUnwindEncoding() local
1310 if (RegOffset != CurOffset - 4) { in generateCompactUnwindEncoding()
1313 << RegOffset << " but only supported at " in generateCompactUnwindEncoding()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 4044 SDValue Base, RegOffset, ImmOffset; in Select() local
4047 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
4048 if (RegOffset != CurDAG->getRegister(0, MVT::i32)) { in Select()
4054 RegOffset = CurDAG->getRegister(0, MVT::i32); in Select()
4056 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select()
4073 SDValue Base, RegOffset, ImmOffset; in Select() local
4076 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
4077 if (RegOffset != CurDAG->getRegister(0, MVT::i32)) { in Select()
4083 RegOffset = CurDAG->getRegister(0, MVT::i32); in Select()
4087 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select()
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