Searched refs:RegOffset (Results 1 – 10 of 10) sorted by relevance
/freebsd/sys/dev/mps/ |
H A D | mps_ioctl.h | 335 uint32_t RegOffset; member
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H A D | mps_user.c | 2081 data->RegData = mps_regread(sc, data->RegOffset); in mps_user_reg_access() 2085 mps_regwrite(sc, data->RegOffset, data->RegData); in mps_user_reg_access()
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/freebsd/sys/dev/mpr/ |
H A D | mpr_ioctl.h | 334 uint32_t RegOffset; member
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H A D | mpr_user.c | 2193 data->RegData = mpr_regread(sc, data->RegOffset); in mpr_user_reg_access() 2197 mpr_regwrite(sc, data->RegOffset, data->RegData); in mpr_user_reg_access()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
H A D | SystemZ.cpp | 353 llvm::Value *RegOffset = in EmitVAArg() local 360 CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, RegOffset, "raw_reg_addr"), in EmitVAArg()
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H A D | PPC.cpp | 511 llvm::Value *RegOffset = in EmitVAArg() local 514 CGF.Int8Ty, RegAddr.emitRawPointer(CGF), RegOffset), in EmitVAArg()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DwarfExpression.cpp | 126 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); in addMachineReg() local 129 setSubRegisterPiece(Size, RegOffset); in addMachineReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.cpp | 1517 for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e; in buildSpillLoadStore() local 1518 ++i, RegOffset += EltSize) { in buildSpillLoadStore() 1545 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore() 1572 for (int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS, in buildSpillLoadStore() 1573 LaneE = RegOffset / 4; in buildSpillLoadStore() 1606 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore() 1638 MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(RegOffset); in buildSpillLoadStore() 1641 commonAlignment(Alignment, RegOffset)); in buildSpillLoadStore() 1669 MIB.addImm(Offset + RegOffset); in buildSpillLoadStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackend.cpp | 1279 int RegOffset = Offset->second; in generateCompactUnwindEncoding() local 1280 if (RegOffset != CurOffset - 4) { in generateCompactUnwindEncoding() 1283 << RegOffset << " but only supported at " in generateCompactUnwindEncoding()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 4050 SDValue Base, RegOffset, ImmOffset; in Select() local 4053 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select() 4054 if (RegOffset != CurDAG->getRegister(0, MVT::i32)) { in Select() 4060 RegOffset = CurDAG->getRegister(0, MVT::i32); in Select() 4062 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select() 4079 SDValue Base, RegOffset, ImmOffset; in Select() local 4082 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select() 4083 if (RegOffset != CurDAG->getRegister(0, MVT::i32)) { in Select() 4089 RegOffset = CurDAG->getRegister(0, MVT::i32); in Select() 4093 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select()
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