| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/LowLevel/ |
| H A D | DWARFUnwindTable.cpp | 40 UnwindLocation::createIsRegisterPlusOffset(uint32_t RegNum, int32_t Offset, in createIsRegisterPlusOffset() argument
42 return {RegPlusOffset, RegNum, Offset, AddrSpace, false}; in createIsRegisterPlusOffset()
46 UnwindLocation::createAtRegisterPlusOffset(uint32_t RegNum, int32_t Offset, in createAtRegisterPlusOffset() argument
48 return {RegPlusOffset, RegNum, Offset, AddrSpace, true}; in createAtRegisterPlusOffset()
70 return RegNum == RHS.RegNum && Offset == RHS.Offset && in operator ==()
141 llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0); in parseRows() local
142 if (!RegNum) in parseRows()
143 return RegNum.takeError(); in parseRows()
145 InitialLocs->getRegisterLocation(*RegNum)) in parseRows()
146 Row.getRegisterLocations().setRegisterLocation(*RegNum, *O); in parseRows()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_mips64.cpp | 34 enum RegNum : uint32_t { enum
104 Address[2] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, in patchSled()
105 RegNum::RN_RA, 0x8); in patchSled()
106 Address[3] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
110 Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
111 RegNum::RN_T9, HigherTracingHookAddr); in patchSled()
113 RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
114 Address[7] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
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| H A D | xray_riscv.cpp | 37 enum RegNum : uint32_t { enum
168 Address[Idx++] = encodeSTypeInstruction(StoreOp, RegNum::RN_SP, in patchSled()
169 RegNum::RN_RA, 3 * XLenBytes); in patchSled()
170 Address[Idx++] = encodeSTypeInstruction(StoreOp, RegNum::RN_SP, in patchSled()
171 RegNum::RN_A0, 2 * XLenBytes); in patchSled()
174 Address[Idx++] = encodeSTypeInstruction(StoreOp, RegNum::RN_SP, in patchSled()
175 RegNum::RN_T1, XLenBytes); in patchSled()
176 Address[Idx++] = encodeUTypeInstruction(PatchOpcodes::PO_LUI, RegNum::RN_T1, in patchSled()
179 encodeITypeInstruction(PatchOpcodes::PO_ADDI, RegNum::RN_T1, in patchSled()
180 RegNum::RN_T1, HigherTracingHookAddr); in patchSled()
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| H A D | xray_loongarch64.cpp | 21 enum RegNum : uint32_t { enum
88 Address[1] = encodeInstruction2RIx(0x29c00000, RegNum::RN_RA, RegNum::RN_SP, in patchSled()
91 0x14000000, RegNum::RN_T0, in patchSled()
94 0x03800000, RegNum::RN_T0, RegNum::RN_T0, in patchSled()
97 0x16000000, RegNum::RN_T0, in patchSled()
100 0x03000000, RegNum::RN_T0, RegNum::RN_T0, in patchSled()
103 encodeInstruction1RI20(0x14000000, RegNum::RN_T1, in patchSled()
106 encodeInstruction2RIx(0x03800000, RegNum::RN_T1, RegNum::RN_T1, in patchSled()
108 Address[8] = encodeInstruction2RIx(0x4c000000, RegNum::RN_RA, RegNum::RN_T0, in patchSled()
110 Address[9] = encodeInstruction2RIx(0x28c00000, RegNum::RN_RA, RegNum::RN_SP, in patchSled()
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| H A D | xray_mips.cpp | 33 enum RegNum : uint32_t { enum
104 Address[2] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, in patchSled()
105 RegNum::RN_RA, 0x4); in patchSled()
106 Address[3] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
110 Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
111 RegNum::RN_T9, LoTracingHookAddr); in patchSled()
112 Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, in patchSled()
114 Address[7] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9, in patchSled()
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| H A D | xray_hexagon.cpp | 37 enum RegNum : uint32_t { enum
43 encodeExtendedTransferImmediate(uint32_t Imm, RegNum DestReg, in encodeExtendedTransferImmediate()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 144 int64_t MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
150 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
152 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
161 std::optional<MCRegister> MCRegisterInfo::getLLVMRegNum(uint64_t RegNum, in getLLVMRegNum() argument
168 DwarfLLVMRegPair Key = {unsigned(RegNum), 0}; in getLLVMRegNum()
170 if (I != M + Size && I->FromReg == RegNum) in getLLVMRegNum()
175 int64_t MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(uint64_t RegNum) const { in getDwarfRegNumFromDwarfEHRegNum()
184 if (std::optional<MCRegister> LRegNum = getLLVMRegNum(RegNum, true)) { in getDwarfRegNumFromDwarfEHRegNum()
187 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
191 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/LowLevel/ |
| H A D | DWARFUnwindTable.h | 60 uint32_t RegNum; /// The register number for Kind == RegPlusOffset. variable
72 : Kind(K), RegNum(InvalidRegisterNumber), Offset(0), in UnwindLocation()
77 : Kind(K), RegNum(Reg), Offset(Off), AddrSpace(AS), Dereference(Deref) {} in UnwindLocation()
80 : Kind(DWARFExpr), RegNum(InvalidRegisterNumber), Offset(0), Expr(E), in UnwindLocation()
124 uint32_t getRegister() const { return RegNum; } in getRegister()
141 void setRegister(uint32_t NewRegNum) { RegNum = NewRegNum; } in setRegister()
176 std::optional<UnwindLocation> getRegisterLocation(uint32_t RegNum) const { in getRegisterLocation() argument
177 auto Pos = Locations.find(RegNum); in getRegisterLocation()
195 void setRegisterLocation(uint32_t RegNum, const UnwindLocation &Location) { in setRegisterLocation() argument
196 Locations.erase(RegNum); in setRegisterLocation()
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| H A D | DWARFCFIProgram.h | 158 auto RegNum = Data.getULEB128(C); in parse() local
163 addInstruction(Opcode, RegNum, CfaOffset, AddressSpace); in parse()
205 uint64_t RegNum = Data.getULEB128(C); in parse() local
206 addInstruction(Opcode, RegNum, 0); in parse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 77 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
83 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
84 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
102 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
103 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
107 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
109 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
128 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
132 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
133 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 169 int64_t NVPTXRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
170 StringRef Name = NVPTXInstPrinter::getRegisterName(RegNum.id()); in getDwarfRegNum()
174 if (RegNum.id() == NVPTX::VRDepot) in getDwarfRegNum()
179 int64_t NVPTXRegisterInfo::getDwarfRegNumForVirtReg(Register RegNum, in getDwarfRegNumForVirtReg() argument
181 assert(RegNum.isVirtual()); in getDwarfRegNumForVirtReg()
182 uint64_t lookup = debugRegisterMap.lookup(RegNum.id()); in getDwarfRegNumForVirtReg()
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| H A D | NVPTXRegisterInfo.h | 74 int64_t getDwarfRegNum(MCRegister RegNum, bool isEH) const override;
75 int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 210 MCRegister RegNum; member
252 return Reg.RegNum; in getReg()
441 Op->Reg.RegNum = Reg; in CreateReg()
1842 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1843 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1845 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
1850 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum); in processInstruction()
1859 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1860 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
1862 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFCFIPrinter.cpp | 29 unsigned RegNum) { in printRegister() argument
31 auto RegName = DumpOpts.GetNameForDWARFReg(RegNum, DumpOpts.IsEH); in printRegister()
37 OS << "reg" << RegNum; in printRegister()
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| H A D | DWARFUnwindTablePrinter.cpp | 24 unsigned RegNum) { in printRegister() argument
26 auto RegName = DumpOpts.GetNameForDWARFReg(RegNum, DumpOpts.IsEH); in printRegister()
32 OS << "reg" << RegNum; in printRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 391 unsigned RegNum; member
417 unsigned RegNum; member
427 unsigned RegNum; member
679 return Reg.RegNum; in getReg()
684 return MatrixReg.RegNum; in getMatrixReg()
709 return VectorList.RegNum; in getVectorListStart()
1245 Reg.RegNum) || in isNeonVectorRegLo()
1247 Reg.RegNum)); in isNeonVectorRegLo()
1253 Reg.RegNum)); in isNeonVectorReg0to7()
1382 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 219 unsigned RegNum = Op.getReg(); in getMachineOpValue() local
221 Value |= RI->getEncodingValue(RegNum); in getMachineOpValue()
223 if (M68kII::isAddressRegister(RegNum)) in getMachineOpValue()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 437 virtual int64_t getDwarfRegNum(MCRegister RegNum, bool isEH) const;
441 std::optional<MCRegister> getLLVMRegNum(uint64_t RegNum, bool isEH) const;
445 int64_t getDwarfRegNumFromDwarfEHRegNum(uint64_t RegNum) const;
449 int getSEHRegNum(MCRegister RegNum) const;
453 int getCodeViewRegNum(MCRegister RegNum) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 172 unsigned RegNum; member
345 return Reg.RegNum; in getReg()
609 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
612 Op->Reg.RegNum = RegNum; in CreateReg()
660 Op.Reg.RegNum = I32Regs[regIdx]; in MorphToI32Reg()
669 Op.Reg.RegNum = F32Regs[regIdx]; in MorphToF32Reg()
678 Op.Reg.RegNum = F128Regs[regIdx / 2]; in MorphToF128Reg()
687 Op.Reg.RegNum = VM512Regs[regIdx / 2]; in MorphToVM512Reg()
699 Op.Reg.RegNum = MISCRegs[regIdx]; in MorphToMISCReg()
821 int RegNum = matchFn(Name); in parseRegisterName() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 195 int RegNum; in getDwarfRegNum() local
197 RegNum = TRI->getDwarfRegNum(SR, false); in getDwarfRegNum()
198 if (RegNum >= 0) in getDwarfRegNum()
202 assert(RegNum >= 0 && isUInt<16>(RegNum) && "Invalid Dwarf register number."); in getDwarfRegNum()
203 return (unsigned)RegNum; in getDwarfRegNum()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFExpressionPrinter.h | 49 std::function<StringRef(uint64_t RegNum, bool IsEH)> GetNameForDWARFReg =
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 157 MCRegister RegNum; member
405 return Reg.RegNum; in getReg()
484 Op->Reg.RegNum = RegNo; in createReg()
632 return Reg.RegNum == Other.Reg.RegNum; in isValidForTie()
1629 Op.Reg.RegNum = convertFPR32ToFPR64(Reg); in validateTargetOperandClass()
1631 (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F15_64)) in validateTargetOperandClass()
1634 (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F31_64)) in validateTargetOperandClass()
1642 Op.Reg.RegNum = MRI->getEncodingValue(Reg) + CSKY::R0_R1; in validateTargetOperandClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 355 MCRegister RegNum; member
463 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; in isV0Reg()
467 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) || in isAnyReg()
468 RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) || in isAnyReg()
469 RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum)); in isAnyReg()
474 Reg.RegNum) || in isAnyRegC()
476 Reg.RegNum)); in isAnyRegC()
490 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); in isGPR()
496 Reg.RegNum); in isGPRPair()
502 Reg.RegNum); in isGPRPairC()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GIMatchTableExecutorImpl.h | 1173 uint16_t RegNum = readU16(); in executeMatchTable() local
1177 OutMIs[InsnID].addDef(RegNum, Flags); in executeMatchTable()
1180 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
1186 uint16_t RegNum = readU16(); in executeMatchTable() local
1188 OutMIs[InsnID].addUse(RegNum, RegState::Implicit); in executeMatchTable()
1191 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
1197 uint16_t RegNum = readU16(); in executeMatchTable() local
1200 OutMIs[InsnID].addReg(RegNum, RegFlags); in executeMatchTable()
1204 << "], " << RegNum << ", " << RegFlags << ")\n"); in executeMatchTable()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/ |
| H A D | sanitizer_linux.cpp | 2369 static uptr GetArmRegister(ucontext_t *ctx, int RegNum) { in GetArmRegister() argument
2370 switch (RegNum) { in GetArmRegister()
2402 return ctx->uc_mcontext.regs[RegNum]; in GetArmRegister()
2407 return ctx->uc_mcontext.__gregs[RegNum]; in GetArmRegister()
2419 static void DumpSingleReg(ucontext_t *ctx, int RegNum) { in DumpSingleReg() argument
2420 const char *RegName = RegNumToRegName(RegNum); in DumpSingleReg()
2426 ctx->uc_mcontext.gregs[RegNum] in DumpSingleReg()
2428 ctx->uc_mcontext.__gregs[RegNum] in DumpSingleReg()
2434 ctx->uc_mcontext.gregs[RegNum] in DumpSingleReg()
2436 ctx->uc_mcontext.__gregs[RegNum] in DumpSingleReg()
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