| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_mips64.cpp | 34 enum RegNum : uint32_t { enum
104 Address[2] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, in patchSled()
105 RegNum::RN_RA, 0x8); in patchSled()
106 Address[3] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
110 Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
111 RegNum::RN_T9, HigherTracingHookAddr); in patchSled()
113 RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
114 Address[7] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
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| H A D | xray_loongarch64.cpp | 21 enum RegNum : uint32_t { enum
88 Address[1] = encodeInstruction2RIx(0x29c00000, RegNum::RN_RA, RegNum::RN_SP, in patchSled()
91 0x14000000, RegNum::RN_T0, in patchSled()
94 0x03800000, RegNum::RN_T0, RegNum::RN_T0, in patchSled()
97 0x16000000, RegNum::RN_T0, in patchSled()
100 0x03000000, RegNum::RN_T0, RegNum::RN_T0, in patchSled()
103 encodeInstruction1RI20(0x14000000, RegNum::RN_T1, in patchSled()
106 encodeInstruction2RIx(0x03800000, RegNum::RN_T1, RegNum::RN_T1, in patchSled()
108 Address[8] = encodeInstruction2RIx(0x4c000000, RegNum::RN_RA, RegNum::RN_T0, in patchSled()
110 Address[9] = encodeInstruction2RIx(0x28c00000, RegNum::RN_RA, RegNum::RN_SP, in patchSled()
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| H A D | xray_mips.cpp | 33 enum RegNum : uint32_t { enum
104 Address[2] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, in patchSled()
105 RegNum::RN_RA, 0x4); in patchSled()
106 Address[3] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
110 Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, in patchSled()
111 RegNum::RN_T9, LoTracingHookAddr); in patchSled()
112 Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, in patchSled()
114 Address[7] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9, in patchSled()
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| H A D | xray_hexagon.cpp | 37 enum RegNum : uint32_t { enum
43 encodeExtendedTransferImmediate(uint32_t Imm, RegNum DestReg, in encodeExtendedTransferImmediate()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 144 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
150 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
152 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
157 std::optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum, in getLLVMRegNum() argument
164 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
166 if (I != M + Size && I->FromReg == RegNum) in getLLVMRegNum()
171 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { in getDwarfRegNumFromDwarfEHRegNum()
180 if (std::optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) { in getDwarfRegNumFromDwarfEHRegNum()
183 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
187 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.cpp | 32 unsigned RegNum) { in printRegister() argument
34 auto RegName = DumpOpts.GetNameForDWARFReg(RegNum, DumpOpts.IsEH); in printRegister()
40 OS << "reg" << RegNum; in printRegister()
62 UnwindLocation::createIsRegisterPlusOffset(uint32_t RegNum, int32_t Offset, in createIsRegisterPlusOffset() argument
64 return {RegPlusOffset, RegNum, Offset, AddrSpace, false}; in createIsRegisterPlusOffset()
68 UnwindLocation::createAtRegisterPlusOffset(uint32_t RegNum, int32_t Offset, in createAtRegisterPlusOffset() argument
70 return {RegPlusOffset, RegNum, Offset, AddrSpace, true}; in createAtRegisterPlusOffset()
103 printRegister(OS, DumpOpts, RegNum); in dump()
142 return RegNum == RHS.RegNum && Offset == RHS.Offset && in operator ==()
325 auto RegNum = Data.getULEB128(C); in parse() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 78 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
84 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
85 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
103 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
104 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
108 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
110 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
129 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
133 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
134 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 213 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
215 return std::make_unique<AVROperand>(RegNum, S, E); in CreateReg()
224 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { in CreateMemri() argument
225 return std::make_unique<AVROperand>(RegNum, Val, S, E); in CreateMemri()
352 int RegNum = matchFn(Name); in parseRegisterName() local
358 if (RegNum == AVR::NoRegister) { in parseRegisterName()
359 RegNum = matchFn(Name.lower()); in parseRegisterName()
361 if (RegNum == AVR::NoRegister) { in parseRegisterName()
362 RegNum = matchFn(Name.upper()); in parseRegisterName()
365 return RegNum; in parseRegisterName()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.h | 68 uint32_t RegNum; /// The register number for Kind == RegPlusOffset. variable
80 : Kind(K), RegNum(InvalidRegisterNumber), Offset(0), in UnwindLocation()
85 : Kind(K), RegNum(Reg), Offset(Off), AddrSpace(AS), Dereference(Deref) {} in UnwindLocation()
88 : Kind(DWARFExpr), RegNum(InvalidRegisterNumber), Offset(0), Expr(E), in UnwindLocation()
132 uint32_t getRegister() const { return RegNum; } in getRegister()
142 void setRegister(uint32_t NewRegNum) { RegNum = NewRegNum; } in setRegister()
192 std::optional<UnwindLocation> getRegisterLocation(uint32_t RegNum) const { in getRegisterLocation() argument
193 auto Pos = Locations.find(RegNum); in getRegisterLocation()
204 void setRegisterLocation(uint32_t RegNum, const UnwindLocation &Location) { in setRegisterLocation() argument
205 Locations.erase(RegNum); in setRegisterLocation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRInstPrinter.cpp | 89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, in getPrettyRegisterName() argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; in getPrettyRegisterName()
98 return getRegisterName(RegNum); in getPrettyRegisterName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 208 unsigned RegNum; member
250 return Reg.RegNum; in getReg()
437 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
439 Op->Reg.RegNum = RegNum; in CreateReg()
1833 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1834 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1836 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
1841 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum); in processInstruction()
1850 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1851 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 200 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
202 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E); in CreateReg()
210 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, in CreateMem() argument
213 return std::make_unique<MSP430Operand>(RegNum, Val, S, E); in CreateMem()
216 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, in CreateIndReg() argument
218 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E); in CreateIndReg()
221 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, in CreatePostIndReg() argument
223 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E); in CreatePostIndReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 383 unsigned RegNum; member
409 unsigned RegNum; member
419 unsigned RegNum; member
663 return Reg.RegNum; in getReg()
668 return MatrixReg.RegNum; in getMatrixReg()
693 return VectorList.RegNum; in getVectorListStart()
1226 Reg.RegNum) || in isNeonVectorRegLo()
1228 Reg.RegNum)); in isNeonVectorRegLo()
1234 Reg.RegNum)); in isNeonVectorReg0to7()
1360 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 205 unsigned RegNum = Op.getReg(); in encodeInstruction()
207 Value |= RI->getEncodingValue(RegNum); in encodeInstruction()
209 if (M68kII::isAddressRegister(RegNum)) in encodeInstruction()
181 unsigned RegNum = Op.getReg(); getMachineOpValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 121 unsigned RegNum; member
156 return Reg.RegNum; in getReg()
592 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, in createReg()
595 Op->Reg.RegNum = RegNum; in createReg()
694 unsigned RegNum; in parseRegister() local
701 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); in parseRegister()
702 if (RegNum == 0) { in parseRegister()
708 return LanaiOperand::createReg(RegNum, Start, End); in parseRegister()
715 bool LanaiAsmParser::parseRegister(MCRegister &RegNum, SMLoc &StartLoc, in parseRegister() argument
722 RegNum = Op->getReg(); in parseRegister()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 421 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
425 std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
429 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
433 int getSEHRegNum(MCRegister RegNum) const;
437 int getCodeViewRegNum(MCRegister RegNum) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 176 unsigned RegNum; member
349 return Reg.RegNum; in getReg()
599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
602 Op->Reg.RegNum = RegNum; in CreateReg()
650 Op.Reg.RegNum = I32Regs[regIdx]; in MorphToI32Reg()
659 Op.Reg.RegNum = F32Regs[regIdx]; in MorphToF32Reg()
668 Op.Reg.RegNum = F128Regs[regIdx / 2]; in MorphToF128Reg()
677 Op.Reg.RegNum = VM512Regs[regIdx / 2]; in MorphToVM512Reg()
689 Op.Reg.RegNum = MISCRegs[regIdx]; in MorphToMISCReg()
811 int RegNum = matchFn(Name); in parseRegisterName() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 157 unsigned RegNum; member
405 return Reg.RegNum; in getReg()
484 Op->Reg.RegNum = RegNo; in createReg()
632 return Reg.RegNum == Other.Reg.RegNum; in isValidForTie()
1631 Op.Reg.RegNum = convertFPR32ToFPR64(Reg); in validateTargetOperandClass()
1633 (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F15_64)) in validateTargetOperandClass()
1636 (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F31_64)) in validateTargetOperandClass()
1644 Op.Reg.RegNum = MRI->getEncodingValue(Reg) + CSKY::R0_R1; in validateTargetOperandClass()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 196 int RegNum; in getDwarfRegNum() local
198 RegNum = TRI->getDwarfRegNum(SR, false); in getDwarfRegNum()
199 if (RegNum >= 0) in getDwarfRegNum()
203 assert(RegNum >= 0 && isUInt<16>(RegNum) && "Invalid Dwarf register number."); in getDwarfRegNum()
204 return (unsigned)RegNum; in getDwarfRegNum()
647 /// uint16 : Dwarf RegNum
653 /// uint16 : Dwarf RegNum
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.h | 47 int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GIMatchTableExecutorImpl.h | 1119 uint16_t RegNum = readU16(); in executeMatchTable() local
1123 OutMIs[InsnID].addDef(RegNum, Flags); in executeMatchTable()
1126 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
1132 uint16_t RegNum = readU16(); in executeMatchTable() local
1134 OutMIs[InsnID].addUse(RegNum, RegState::Implicit); in executeMatchTable()
1137 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
1143 uint16_t RegNum = readU16(); in executeMatchTable() local
1146 OutMIs[InsnID].addReg(RegNum, RegFlags); in executeMatchTable()
1150 << "], " << RegNum << ", " << RegFlags << ")\n"); in executeMatchTable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 291 auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum, in DecodeMoveHRegInstruction()
293 if (30 == RegNum) { in DecodeMoveHRegInstruction()
298 return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder); in DecodeMoveHRegInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 89 unsigned RegNum; member
153 return Reg.RegNum; in getReg()
212 Op->Reg.RegNum = RegNo; in createReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 234 unsigned RegNum; member
325 return Reg.RegNum; in getReg()
470 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() argument
473 Op->Reg.RegNum = RegNum; in CreateReg()
521 Op.Reg.RegNum = IntPairRegs[regIdx / 2]; in MorphToIntPairReg()
532 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
555 Op.Reg.RegNum = Reg; in MorphToQuadReg()
568 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2]; in MorphToCoprocPairReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 865 unsigned RegNum; member
870 unsigned RegNum; member
899 unsigned RegNum; member
1005 return Reg.RegNum; in getReg()
1373 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg.RegNum); in isDReg()
1377 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg.RegNum); in isQReg()
1477 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
2070 VectorList.RegNum); in isVecListTwoMQ()
2080 .contains(VectorList.RegNum)); in isVecListDPair()
2097 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
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