| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRInstPrinter.cpp | 94 MCRegister RegLo = MRI.getSubReg(Reg, AVR::sub_lo); in getPrettyRegisterName() local
95 Reg = (RegLo != AVR::NoRegister) ? RegLo : Reg; in getPrettyRegisterName()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 469 Register RegLo = VA.getLocReg(); in LowerReturn() local
470 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerReturn()
471 Register RegHi = RegLo + 1; in LowerReturn()
473 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn()
475 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); in LowerReturn()
586 Register RegLo = VA.getLocReg(); in LowerCall() local
587 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall()
589 if (RegLo == CSKY::R3) { in LowerCall()
599 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerCall()
600 Register RegHigh = RegLo + 1; in LowerCall()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2962 int64_t RegLo, RegHi; in ParseRegRange() local
2969 if (!parseExpr(RegLo)) in ParseRegRange()
2977 RegHi = RegLo; in ParseRegRange()
2983 if (!isUInt<32>(RegLo)) { in ParseRegRange()
2993 if (RegLo > RegHi) { in ParseRegRange()
2998 if (RegHi == RegLo) { in ParseRegRange()
3009 Num = static_cast<unsigned>(RegLo); in ParseRegRange()
3010 RegWidth = 32 * ((RegHi - RegLo) + 1); in ParseRegRange()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 7390 Register RegLo = VA.getLocReg(); in LowerCall() local
7391 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall()
7655 Register RegLo = VA.getLocReg(); in LowerReturn() local
7658 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn()
7660 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); in LowerReturn()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1965 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
1967 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2457 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
2488 BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo).addReg(RegLo).add(OpLo)); in expandPostRAPseudo()
|
| H A D | SIISelLowering.cpp | 5599 Register RegLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
5600 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B32), RegLo) in EmitInstrWithCustomInserter()
5605 .addReg(RegLo) in EmitInstrWithCustomInserter()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 22583 Register RegLo = VA.getLocReg(); in LowerCall() local
22584 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall()
22870 Register RegLo = VA.getLocReg(); in LowerReturn() local
22873 if (STI.isRegisterReservedByUser(RegLo) || in LowerReturn()
22879 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn()
22881 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); in LowerReturn()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4352 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local
4354 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32); in LowerFormalArguments_32SVR4()
|