| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 23 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
26 if (MCRegister Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
40 if (MCRegister Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
197 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
200 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
214 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
[all …]
|
| H A D | Thumb2ITBlockPass.cpp | 80 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
81 RegList LocalDefs; in INITIALIZE_PASS()
82 RegList LocalUses; in INITIALIZE_PASS()
96 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
|
| H A D | ARMAsmPrinter.cpp | 1237 SmallVector<MCRegister, 4> RegList; in EmitUnwindingInstruction() local
1274 assert(RegList.empty() && in EmitUnwindingInstruction()
1286 RegList.push_back(Reg); in EmitUnwindingInstruction()
1297 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1305 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1309 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1316 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
|
| H A D | ARMBaseInstrInfo.cpp | 2402 SmallVector<MachineOperand, 4> RegList; in tryFoldSPUpdateIntoPushPop() local
2411 RegList.push_back(MO); in tryFoldSPUpdateIntoPushPop()
2430 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2452 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
2468 for (const MachineOperand &MO : llvm::reverse(RegList)) in tryFoldSPUpdateIntoPushPop()
|
| H A D | ARMInstrInfo.td | 621 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 142 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
144 RegList = XRegList; in CC_AArch64_Custom_Block()
146 RegList = HRegList; in CC_AArch64_Custom_Block()
148 RegList = SRegList; in CC_AArch64_Custom_Block()
150 RegList = DRegList; in CC_AArch64_Custom_Block()
152 RegList = QRegList; in CC_AArch64_Custom_Block()
158 RegList = PRegList; in CC_AArch64_Custom_Block()
160 RegList = ZRegList; in CC_AArch64_Custom_Block()
180 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg); in CC_AArch64_Custom_Block()
207 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
|
| H A D | AArch64RegisterInfo.cpp | 683 auto HasReg = [](ArrayRef<MCRegister> RegList, MCRegister Reg) { in isArgumentRegister() argument
684 return llvm::is_contained(RegList, Reg); in isArgumentRegister()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.cpp | 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
40 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
101 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
243 static const unsigned NumRegs = std::size(RegList); in CC_X86_32_MCUInReg()
261 if (MCRegister Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 191 RegListOp RegList; member
218 RegList = o.RegList; in CSKYOperand()
415 return RegList; in getRegList()
503 Op->RegList.List1From = 0; in createRegList()
504 Op->RegList.List1To = 0; in createRegList()
505 Op->RegList.List2From = 0; in createRegList()
506 Op->RegList.List2To = 0; in createRegList()
507 Op->RegList.List3From = 0; in createRegList()
508 Op->RegList.List3To = 0; in createRegList()
509 Op->RegList.List4From = 0; in createRegList()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 236 const ListInit *RegList = Action->getValueAsListInit("RegList"); in emitAction() local
237 for (unsigned I = 0, E = RegList->size(); I != E; ++I) { in emitAction()
238 std::string Name = getQualifiedRegisterName(RegList->getElement(I)); in emitAction()
244 EmitAllocateReg({RegList}, {"RegList"}); in emitAction()
252 const ListInit *RegList = Action->getValueAsListInit("RegList"); in emitAction() local
254 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in emitAction()
258 EmitAllocateReg({RegList, ShadowRegList}, {"RegList", "RegList"}); in emitAction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 85 void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
172 const SmallVectorImpl<MCRegister> &RegList, bool isVector) { in emitRegSave() argument
173 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
179 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
181 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
183 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
428 void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
499 void emitRegSave(const SmallVectorImpl<MCRegister> &RegList, bool isVector);
772 const SmallVectorImpl<MCRegister> &RegList, bool isVector) { in emitRegSave() argument
773 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
[all …]
|
| H A D | ARMTargetStreamer.cpp | 99 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<MCRegister> &RegList, in emitRegSave() argument
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.td | 113 list<Register> RegList = regList;
120 list<string> RegList = regList;
127 list<Register> RegList = regList;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 349 RegList, enumerator
411 RegListOp RegList; member
448 case KindTy::RegList: in RISCVOperand()
449 RegList = o.RegList; in RISCVOperand()
482 bool isRegList() const { return Kind == KindTy::RegList; } in isRegList()
484 return Kind == KindTy::RegList && RegList.Encoding != RISCVZC::RA; in isRegListS0()
1065 case KindTy::RegList: in print()
1067 RISCVZC::printRegList(RegList.Encoding, OS); in print()
1156 auto Op = std::make_unique<RISCVOperand>(KindTy::RegList); in createRegList()
1157 Op->RegList.Encoding = RlistEncode; in createRegList()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 348 ArrayRef<MCPhysReg> RegList; in AnalyzeArguments() local
353 RegList = BuiltinRegList; in AnalyzeArguments()
356 RegList = CRegList; in AnalyzeArguments()
409 MCRegister Reg = State.AllocateReg(RegList); in AnalyzeArguments()
417 MCRegister Reg = State.AllocateReg(RegList); in AnalyzeArguments()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2634 const SmallVectorImpl<MCRegister> &RegList = getRegList(); in addRegListOperands() local
2635 for (MCRegister Reg : RegList) in addRegListOperands()
2641 const SmallVectorImpl<MCRegister> &RegList = getRegList(); in addRegListWithAPSROperands() local
2642 for (MCRegister Reg : RegList) in addRegListWithAPSROperands()
4114 const SmallVectorImpl<MCRegister> &RegList = getRegList(); in print() local
4115 for (auto I = RegList.begin(), E = RegList.end(); I != E;) { in print()
7757 auto &RegList = Op.getRegList(); in validateInstruction() local
7759 if (RegList.size() == 32 && !hasV8_1MMainline()) { in validateInstruction()
7763 if (hasD32() && RegList.size() != 32) { in validateInstruction()
7767 if (!hasD32() && (RegList.size() != 16 && RegList.size() != 32)) { in validateInstruction()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZc.td | 39 let Name = "RegList";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 63 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Split_64() local
67 if (Register Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
77 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
89 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Ret_Split_64() local
94 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
100 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 791 delete RegList.List; in ~MipsOperand()
834 struct RegListOp RegList; member
1376 int Size = RegList.List->size(); in isRegList16()
1380 unsigned R0 = RegList.List->front(); in isRegList16()
1381 unsigned R1 = RegList.List->back(); in isRegList16()
1386 int PrevReg = *RegList.List->begin(); in isRegList16()
1388 int Reg = (*(RegList.List))[i]; in isRegList16()
1452 return *(RegList.List); in getRegList()
1556 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); in CreateRegList()
1686 for (auto Reg : (*RegList.List)) in print()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCStreamer.h | 151 virtual void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 520 let Name = "RegList";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.td | 447 let Name = "RegList";
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/ |
| H A D | DemangleTestCases.inc | 24629 …signed int&, llvm::MVT&, llvm::MVT&, llvm::CCValAssign::LocInfo&, llvm::CCState&, bool)::RegList"},
24666 …signed int&, llvm::MVT&, llvm::MVT&, llvm::CCValAssign::LocInfo&, llvm::CCState&, bool)::RegList"},
|