| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
197 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
200 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
214 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
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| H A D | Thumb2ITBlockPass.cpp | 83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
84 RegList LocalDefs; in INITIALIZE_PASS()
85 RegList LocalUses; in INITIALIZE_PASS()
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
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| H A D | ARMAsmPrinter.cpp | 1222 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
1259 assert(RegList.empty() && in EmitUnwindingInstruction()
1271 RegList.push_back(Reg); in EmitUnwindingInstruction()
1282 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1290 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1294 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1301 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
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| H A D | ARMBaseInstrInfo.cpp | 2559 SmallVector<MachineOperand, 4> RegList; in tryFoldSPUpdateIntoPushPop() local
2568 RegList.push_back(MO); in tryFoldSPUpdateIntoPushPop()
2587 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2609 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
2625 for (const MachineOperand &MO : llvm::reverse(RegList)) in tryFoldSPUpdateIntoPushPop()
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| H A D | ARMInstrInfo.td | 601 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 143 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
145 RegList = XRegList; in CC_AArch64_Custom_Block()
147 RegList = HRegList; in CC_AArch64_Custom_Block()
149 RegList = SRegList; in CC_AArch64_Custom_Block()
151 RegList = DRegList; in CC_AArch64_Custom_Block()
153 RegList = QRegList; in CC_AArch64_Custom_Block()
159 RegList = PRegList; in CC_AArch64_Custom_Block()
161 RegList = ZRegList; in CC_AArch64_Custom_Block()
181 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg); in CC_AArch64_Custom_Block()
208 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
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| H A D | AArch64RegisterInfo.cpp | 617 auto HasReg = [](ArrayRef<MCRegister> RegList, MCRegister Reg) { in isArgumentRegister() argument
618 return llvm::is_contained(RegList, Reg); in isArgumentRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.cpp | 34 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
41 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
97 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister()
102 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
243 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
244 static const unsigned NumRegs = std::size(RegList); in CC_X86_32_MCUInReg()
262 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
278 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
283 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, CC_X86_32_RegCall_Assign2Regs() local
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); CC_X86_VectorCallAssignRegister() local
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; CC_X86_32_MCUInReg() local
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 160 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
161 if (RegList->size() == 1) { in EmitAction()
162 std::string Name = getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
174 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
175 std::string Name = getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
213 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
215 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in EmitAction()
219 if (RegList->size() == 1) { in EmitAction()
221 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
232 for (unsigned i = 0, e = RegList->size(); i != e; ++i) in EmitAction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 191 RegListOp RegList; member
218 RegList = o.RegList; in CSKYOperand()
415 return RegList; in getRegList()
503 Op->RegList.List1From = 0; in createRegList()
504 Op->RegList.List1To = 0; in createRegList()
505 Op->RegList.List2From = 0; in createRegList()
506 Op->RegList.List2To = 0; in createRegList()
507 Op->RegList.List3From = 0; in createRegList()
508 Op->RegList.List3To = 0; in createRegList()
509 Op->RegList.List4From = 0; in createRegList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 84 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
166 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
168 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
174 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
176 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
178 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
405 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
473 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
767 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
769 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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| H A D | ARMTargetStreamer.cpp | 99 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.td | 113 list<Register> RegList = regList;
120 list<Register> RegList = regList;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 469 ArrayRef<MCPhysReg> RegList; in AnalyzeArguments() local
474 RegList = BuiltinRegList; in AnalyzeArguments()
477 RegList = CRegList; in AnalyzeArguments()
530 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
538 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2633 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListOperands() local
2634 for (unsigned Reg : RegList) in addRegListOperands()
2640 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListWithAPSROperands() local
2641 for (unsigned Reg : RegList) in addRegListWithAPSROperands()
4106 const SmallVectorImpl<unsigned> &RegList = getRegList(); in print() local
4108 I = RegList.begin(), E = RegList.end(); I != E; ) { in print()
7725 auto &RegList = Op.getRegList(); in validateInstruction() local
7727 if (RegList.size() == 32 && !hasV8_1MMainline()) { in validateInstruction()
7731 if (hasD32() && RegList.size() != 32) { in validateInstruction()
7735 if (!hasD32() && (RegList.size() != 16 && RegList.size() != 32)) { in validateInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 61 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Split_64() local
65 if (Register Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
75 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
87 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Ret_Split_64() local
92 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
98 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 851 delete RegList.List; in ~MipsOperand()
894 struct RegListOp RegList; member
1424 int Size = RegList.List->size(); in isRegList16()
1428 unsigned R0 = RegList.List->front(); in isRegList16()
1429 unsigned R1 = RegList.List->back(); in isRegList16()
1434 int PrevReg = *RegList.List->begin(); in isRegList16()
1436 int Reg = (*(RegList.List))[i]; in isRegList16()
1500 return *(RegList.List); in getRegList()
1604 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); in CreateRegList()
1734 for (auto Reg : (*RegList.List)) in print()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCStreamer.h | 151 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 520 let Name = "RegList";
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.td | 447 let Name = "RegList";
|