Searched refs:RegLR (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 289 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR in lowerGETTLSAddrAndEmitMCInsts() local
307 emitSIC(*OutStreamer, RegLR, STI); in lowerGETTLSAddrAndEmitMCInsts()
309 emitLEASLrri(*OutStreamer, RegS0, RegLR, hiImm, RegS0, STI); in lowerGETTLSAddrAndEmitMCInsts()
317 emitLEASLrri(*OutStreamer, RegS12, RegLR, hiImm2, RegS12, STI); in lowerGETTLSAddrAndEmitMCInsts()
318 emitBSIC(*OutStreamer, RegLR, RegS12, STI); in lowerGETTLSAddrAndEmitMCInsts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 39 RegLR = 3 enumerator
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| H A D | ARMBaseRegisterInfo.cpp | 380 case ARMRI::RegLR: in getRegAllocationHints()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 1052 MF->getRegInfo().setRegAllocationHint(R, ARMRI::RegLR, 0); in HintDoLoopStartReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.cpp | 3916 LiveRange &RegLR, in checkMergingChangesDbgValuesImpl() argument
3932 auto ShouldUndef = [&RegVals, &RegLR, &LastUndefResult, in checkMergingChangesDbgValuesImpl()
3944 auto OtherIt = RegLR.find(Idx); in checkMergingChangesDbgValuesImpl()
3945 if (OtherIt == RegLR.end()) in checkMergingChangesDbgValuesImpl()
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