| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 123 MCRegister matchRegisterName(const AsmToken &Tok, unsigned &RegKind);
863 unsigned RegKind = SparcOperand::rk_None; in tryParseRegister() local
864 Reg = matchRegisterName(Tok, RegKind); in tryParseRegister()
1273 unsigned RegKind; in parseOperand() local
1274 MCRegister Reg = matchRegisterName(Parser.getTok(), RegKind); in parseOperand()
1280 Operands.push_back(SparcOperand::CreateReg(Reg, RegKind, S, E)); in parseOperand()
1370 unsigned RegKind; in parseSparcAsmOperand() local
1371 if (MCRegister Reg = matchRegisterName(Parser.getTok(), RegKind)) { in parseSparcAsmOperand()
1378 Op = SparcOperand::CreateReg(Reg, RegKind, S, E); in parseSparcAsmOperand()
1443 unsigned &RegKind) { in matchRegisterName() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 67 enum class RegKind { enum
90 StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
166 unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
233 unsigned getNumRegsForRegKind(RegKind K);
248 RegKind MatchKind);
277 template <RegKind RK>
281 template <RegKind VectorKind>
384 RegKind Kind;
424 RegKind RegisterKind;
1216 return Kind == k_Register && Reg.Kind == RegKind::Scalar; in isScalarReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 123 unsigned RegKind : 4; member
189 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
194 Op->Mem.RegKind = RegKind; in createMem()
227 bool isReg(RegisterKind RegKind) const { in isReg()
228 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
268 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
269 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
271 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
272 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true); in isMemDisp12()
274 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1280 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, in usesRegister() argument
1282 switch (RegKind) { in usesRegister()
1362 RegisterKind RegKind, unsigned Reg1, SMLoc Loc);
1363 bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1366 bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1369 unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1372 unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1375 unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1378 unsigned getRegularReg(RegisterKind RegKind, unsigned RegNum, unsigned SubReg,
1383 std::optional<StringRef> getGprCountSymbolName(RegisterKind RegKind);
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/ABI/X86/ |
| H A D | ABIX86.cpp | 50 enum RegKind { enum
64 RegKind subreg_kind;
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMWinEHPrinter.cpp | 885 int RegKind = (OC[Offset + 2] & 0xC0) >> 6; in opcode_save_any_reg()
892 if (!Writeback && !Paired && RegKind != 2) in opcode_save_any_reg()
906 if (RegKind == 0) in opcode_save_any_reg()
908 if ((OC[Offset + 1] & 0x80) == 0x80 || RegKind == 3 || Reg > MaxReg) { in opcode_save_any_reg()
927 if (RegKind == 1) { in opcode_save_any_reg()
929 } else if (RegKind == 2) { in opcode_save_any_reg()
884 int RegKind = (OC[Offset + 2] & 0xC0) >> 6; opcode_save_any_reg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 592 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
604 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
614 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
946 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
987 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
1065 let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";
1066 let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "
1097 "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
1232 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
1234 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.h | 31 enum RegKind { enum
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 447 bool validateMSAIndex(int Val, int RegKind);
813 enum RegKind { enum in __anona2e40b320211::MipsOperand
871 RegKind Kind; /// Bitfield of the kinds it could possibly be
901 RegKind RegKind, in CreateReg() argument
908 Op->RegIdx.Kind = RegKind; in CreateReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorize.cpp | 4227 TargetTransformInfo::RegisterKind RegKind = in getMaximizedVFForTarget() local
4233 (TTI.shouldMaximizeVectorBandwidth(RegKind) || in getMaximizedVFForTarget()
6794 TargetTransformInfo::RegisterKind RegKind = in determineVPlanVF() local
6799 TypeSize RegSize = TTI.getRegisterBitWidth(RegKind); in determineVPlanVF()
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