| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 123 MCRegister matchRegisterName(const AsmToken &Tok, unsigned &RegKind);
951 unsigned RegKind = SparcOperand::rk_None; in tryParseRegister() local
952 Reg = matchRegisterName(Tok, RegKind); in tryParseRegister()
1356 unsigned RegKind; in parseOperand() local
1357 MCRegister Reg = matchRegisterName(Parser.getTok(), RegKind); in parseOperand()
1363 Operands.push_back(SparcOperand::CreateReg(Reg, RegKind, S, E)); in parseOperand()
1452 unsigned RegKind; in parseSparcAsmOperand() local
1453 if (MCRegister Reg = matchRegisterName(Parser.getTok(), RegKind)) { in parseSparcAsmOperand()
1460 Op = SparcOperand::CreateReg(Reg, RegKind, S, E); in parseSparcAsmOperand()
1513 unsigned &RegKind) { in matchRegisterName() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 68 enum class RegKind { enum
91 StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
167 unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
241 unsigned getNumRegsForRegKind(RegKind K);
256 RegKind MatchKind);
285 template <RegKind RK>
289 template <RegKind VectorKind>
392 RegKind Kind;
432 RegKind RegisterKind;
1235 return Kind == k_Register && Reg.Kind == RegKind::Scalar; in isScalarReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 128 unsigned RegKind : 4; member
194 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
199 Op->Mem.RegKind = RegKind; in createMem()
232 bool isReg(RegisterKind RegKind) const { in isReg()
233 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
273 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
274 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
276 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
277 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true); in isMemDisp12()
279 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1333 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, in usesRegister() argument
1335 switch (RegKind) { in usesRegister()
1415 RegisterKind RegKind, MCRegister Reg1, SMLoc Loc);
1416 bool ParseAMDGPURegister(RegisterKind &RegKind, MCRegister &Reg,
1419 bool ParseAMDGPURegister(RegisterKind &RegKind, MCRegister &Reg,
1422 MCRegister ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1425 MCRegister ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1428 MCRegister ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1432 MCRegister getRegularReg(RegisterKind RegKind, unsigned RegNum,
1437 std::optional<StringRef> getGprCountSymbolName(RegisterKind RegKind);
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/ABI/X86/ |
| H A D | ABIX86.cpp | 50 enum RegKind { enum
64 RegKind subreg_kind;
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMWinEHPrinter.cpp | 914 int RegKind = (OC[Offset + 2] & 0xC0) >> 6; in opcode_save_any_reg() local
921 if (!Writeback && !Paired && RegKind != 2) in opcode_save_any_reg()
935 if (RegKind == 0) in opcode_save_any_reg()
937 if ((OC[Offset + 1] & 0x80) == 0x80 || RegKind == 3 || Reg > MaxReg) { in opcode_save_any_reg()
956 if (RegKind == 1) { in opcode_save_any_reg()
958 } else if (RegKind == 2) { in opcode_save_any_reg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 640 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
652 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
662 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
673 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ", true>";
1015 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
1056 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
1129 let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";
1130 let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "
1161 "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
1329 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 65 unsigned RegKind = getRegKind(RC, STI); in inc() local
69 unsigned TupleIdx = TOTAL_KINDS + RegKind; in inc()
92 Value[RegKind] += Sign; in inc()
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| H A D | GCNRegPressure.h | 32 enum RegKind { SGPR, VGPR, AGPR, TOTAL_KINDS }; enum
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorize.cpp | 948 bool useMaxBandwidth(TargetTransformInfo::RegisterKind RegKind);
3842 TargetTransformInfo::RegisterKind RegKind) { in useMaxBandwidth() argument
3844 (TTI.shouldMaximizeVectorBandwidth(RegKind) || in useMaxBandwidth()
3910 TargetTransformInfo::RegisterKind RegKind = in getMaximizedVFForTarget() local
3914 if (useMaxBandwidth(RegKind)) { in getMaximizedVFForTarget()
6579 TargetTransformInfo::RegisterKind RegKind = in determineVPlanVF() local
6584 TypeSize RegSize = TTI.getRegisterBitWidth(RegKind); in determineVPlanVF()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 445 bool validateMSAIndex(int Val, int RegKind);
753 enum RegKind { enum in __anona2e40b320211::MipsOperand
811 RegKind Kind; /// Bitfield of the kinds it could possibly be
841 RegKind RegKind, in CreateReg() argument
848 Op->RegIdx.Kind = RegKind; in CreateReg()
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