| /freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 116 MCPhysReg RegID = WS.getRegisterID(); in onInstructionExecuted() local
120 if (!RegID) in onInstructionExecuted()
127 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; in onInstructionExecuted()
128 if (RenameAs && RenameAs != RegID) in onInstructionExecuted()
129 RegID = RenameAs; in onInstructionExecuted()
131 WriteRef &WR = RegisterMappings[RegID].first; in onInstructionExecuted()
135 for (MCPhysReg I : MRI.subregs(RegID)) { in onInstructionExecuted()
144 for (MCPhysReg I : MRI.superregs(RegID)) { in onInstructionExecuted()
236 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite() local
240 if (!RegID) in addRegisterWrite()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLatencyMutations.cpp | 721 const MachineInstr *DstMI, unsigned RegID,
751 unsigned RegID, in modifyMixedWidthFP() argument
759 if (Register::isVirtualRegister(RegID)) { in modifyMixedWidthFP()
763 if (OP.isReg() && OP.isDef() && OP.getReg() == RegID && in modifyMixedWidthFP()
769 if (OP.isReg() && OP.isDef() && OP.getReg() == RegID && in modifyMixedWidthFP()
779 if (OP.isReg() && OP.isDef() && OP.getReg() == RegID && in modifyMixedWidthFP()
785 if (OP.isReg() && OP.isUse() && OP.getReg() == RegID && in modifyMixedWidthFP()
791 if (OP.isReg() && OP.isUse() && OP.getReg() == RegID && in modifyMixedWidthFP()
801 if (OP.isReg() && OP.isUse() && OP.getReg() == RegID && in modifyMixedWidthFP()
805 } else if (Register::isPhysicalRegister(RegID)) { in modifyMixedWidthFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchAsmPrinter.cpp | 101 unsigned RegID = MO.getReg().id(), FirstReg; in PrintAsmOperand() local
102 if (RegID >= LoongArch::XR0 && RegID <= LoongArch::XR31) in PrintAsmOperand()
104 else if (RegID >= LoongArch::VR0 && RegID <= LoongArch::VR31) in PrintAsmOperand()
106 else if (RegID >= LoongArch::F0_64 && RegID <= LoongArch::F31_64) in PrintAsmOperand()
108 else if (RegID >= LoongArch::F0 && RegID <= LoongArch::F31) in PrintAsmOperand()
114 RegID - FirstReg + in PrintAsmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | Instruction.cpp | 21 void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID, in writeStartEvent() argument
24 CRD.RegID = RegID; in writeStartEvent()
30 void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID, in writeStartEvent() argument
43 CRD.RegID = RegID; in writeStartEvent()
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| H A D | InstrBuilder.cpp | 728 MCPhysReg RegID = 0; in createInstruction() local
737 RegID = Op.getReg().id(); in createInstruction()
740 RegID = RD.RegisterID; in createInstruction()
744 if (!RegID) in createInstruction()
750 NewIS->getUses()[Idx] = ReadState(RD, RegID); in createInstruction()
753 NewIS->getUses().emplace_back(RD, RegID); in createInstruction()
802 RegID = WD.isImplicitWrite() ? WD.RegisterID in createInstruction()
806 if ((WD.IsOptionalDef && !RegID) || MRI.isConstant(RegID)) { in createInstruction()
811 assert(RegID && "Expected a valid register ID!"); in createInstruction()
814 WriteState(WD, RegID, in createInstruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 188 MCPhysReg RegID; member
249 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
251 : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),
262 void setRegisterID(const MCPhysReg RegID) { RegisterID = RegID; } in setRegisterID() argument
304 LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
357 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) in ReadState() argument
358 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0), in ReadState()
376 LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | BottleneckAnalysis.h | 257 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, in addRegisterDep() argument
259 addDependency(From, To, {DependencyEdge::DT_REGISTER, RegID, Cost}); in addRegisterDep()
319 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy);
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| H A D | BottleneckAnalysis.cpp | 453 unsigned RegID, unsigned Cost) { in addRegisterDep() argument
457 DG.addRegisterDep(From, To + SourceSize, RegID, Cost); in addRegisterDep()
458 DG.addRegisterDep(From + SourceSize, To + (SourceSize * 2), RegID, Cost); in addRegisterDep()
461 DG.addRegisterDep(From + SourceSize, To + SourceSize, RegID, Cost); in addRegisterDep()
522 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 1153 unsigned RegID = MRI.getRegClass(VirtReg)->getID(); in getRegAllocationHints() local
1154 if (RegID == AArch64::ZPR2StridedOrContiguousRegClassID || in getRegAllocationHints()
1155 RegID == AArch64::ZPR4StridedOrContiguousRegClassID) { in getRegAllocationHints()
1165 switch (RegID) { in getRegAllocationHints()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 548 auto ClearsSuperReg = [=](unsigned RegID) { in clearsSuperRegisters() argument
553 if (GR32RC.contains(RegID)) in clearsSuperRegisters()
564 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); in clearsSuperRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MLRegallocEvictAdvisor.cpp | |
| H A D | MLRegAllocEvictAdvisor.cpp | 366 using RegID = unsigned; typedef in __anonb6cddc090111::MLEvictAdvisor
367 mutable DenseMap<RegID, LIFeatureComponents> CachedFeatures;
886 RegID ID = LI.reg().id(); in getLIFeatureComponents()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 9018 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr in LowerINTRINSIC_WO_CHAIN() local
9021 return getPreloadedValue(DAG, *MFI, VT, RegID); in LowerINTRINSIC_WO_CHAIN()
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