| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 64 SmallSet<unsigned, 32> &RegDefs,
70 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
145 SmallSet<unsigned, 32> RegDefs; in findDelayInstr() local
148 insertDefsUses(Slot, RegDefs, RegUses); in findDelayInstr()
166 if (delayHasHazard(FI, SawLoad, SawStore, RegDefs, RegUses)) { in findDelayInstr()
167 insertDefsUses(FI, RegDefs, RegUses); in findDelayInstr()
177 bool &SawStore, SmallSet<unsigned, 32> &RegDefs, in delayHasHazard() argument
209 if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg)) in delayHasHazard()
214 if (isRegInSet(RegDefs, Reg)) in delayHasHazard()
223 SmallSet<unsigned, 32> &RegDefs, in insertDefsUses() argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 65 SmallSet<unsigned, 32>& RegDefs,
69 SmallSet<unsigned, 32>& RegDefs,
77 SmallSet<unsigned, 32> &RegDefs,
167 SmallSet<unsigned, 32> RegDefs; in findDelayInstr() local
195 insertCallDefsUses(slot, RegDefs, RegUses); in findDelayInstr()
197 insertDefsUses(slot, RegDefs, RegUses); in findDelayInstr()
217 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) { in findDelayInstr()
218 insertDefsUses(I, RegDefs, RegUses); in findDelayInstr()
230 SmallSet<unsigned, 32> &RegDefs, in delayHasHazard() argument
259 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg)) in delayHasHazard()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineLateInstrsCleanup.cpp | 52 std::vector<Reg2MIMap> RegDefs; member in __anon95a8ee9a0111::MachineLateInstrsCleanup
119 RegDefs.clear(); in run()
120 RegDefs.resize(MF.getNumBlockIDs()); in run()
151 Reg2MIMap &MBBDefs = RegDefs[MBB->getNumber()]; in clearKillsForDef()
204 Reg2MIMap &MBBDefs = RegDefs[MBB->getNumber()]; in processBlock()
211 for (auto [Reg, DefMI] : RegDefs[FirstPred->getNumber()]) in processBlock()
215 return RegDefs[Pred->getNumber()].hasIdentical(Reg, DefMI); in processBlock()
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| H A D | MachineDebugify.cpp | 138 SmallVector<MachineOperand *, 4> RegDefs; in applyDebugifyMetadataToMachineFunction() local
141 RegDefs.push_back(&MO); in applyDebugifyMetadataToMachineFunction()
142 for (MachineOperand *MO : RegDefs) in applyDebugifyMetadataToMachineFunction()
147 if (RegDefs.empty()) { in applyDebugifyMetadataToMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHazardRecognizer.cpp | 35 RegDefs.clear(); in Reset()
82 RegDefs.clear(); in AdvanceCycle()
109 return MO.isReg() && RegDefs.contains(MO.getReg()); in isNewStore()
121 RegDefs.insert(MO.getReg()); in EmitInstruction()
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| H A D | HexagonHazardRecognizer.h | 41 SmallSet<unsigned, 8> RegDefs; variable
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| H A D | HexagonLoadStoreWidening.cpp | 274 DenseSet<Register> &RegDefs, in addDefsUsesToList() argument
280 RegDefs.insert(Op.getReg()); in addDefsUsesToList()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/ |
| H A D | DispatchStage.cpp | 46 SmallVector<MCPhysReg, 4> RegDefs; in checkPRF() local
48 RegDefs.emplace_back(RegDef.getRegisterID()); in checkPRF()
50 const unsigned RegisterMask = PRF.isAvailable(RegDefs); in checkPRF()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 904 DenseSet<Register> &RegDefs, in addDefsUsesToList() argument
910 RegDefs.insert(Op.getReg()); in addDefsUsesToList()
1224 DenseSet<Register> RegDefs; in checkAndPrepareMerge() local
1229 addDefsUsesToList(*Paired.I, RegDefs, RegUses); in checkAndPrepareMerge()
1231 if (!canSwapInstructions(RegDefs, RegUses, *Paired.I, *MBBI)) in checkAndPrepareMerge()
1237 addDefsUsesToList(*CI.I, RegDefs, RegUses); in checkAndPrepareMerge()
1239 if (!canSwapInstructions(RegDefs, RegUses, *CI.I, *MBBI)) in checkAndPrepareMerge()
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