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Searched refs:RegClasses (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp930 std::list<CodeGenRegisterClass> &RegClasses = RegBank.getRegClasses(); in computeSubClasses() local
932 const size_t NumRegClasses = RegClasses.size(); in computeSubClasses()
934 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
942 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { in computeSubClasses()
959 for (auto &RC : RegClasses) { in computeSubClasses()
961 auto I = RegClasses.begin(); in computeSubClasses()
975 for (CodeGenRegisterClass &RC : RegClasses) in computeSubClasses()
994 std::list<CodeGenRegisterClass> &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs() local
1003 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs()
1013 for (auto &RC : RegClasses) { in getMatchingSubClassWithSubRegs()
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H A DCodeGenTarget.cpp104 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace() local
105 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; in getRegNamespace()
H A DCodeGenRegisters.h636 std::list<CodeGenRegisterClass> RegClasses; variable
680 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
800 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
803 return RegClasses; in getRegClasses()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td494 // a list of register classes (see field `RegClasses`). An empty list of
498 // A register R can be renamed if its register class appears in the `RegClasses`
503 // However, V is only renamed if its register class is part of `RegClasses`.
514 // register class that is in `RegClasses`.
556 list<RegisterClass> RegClasses = Classes;