| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 30 const RegisterClassInfo &RegClassInfo, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | BreakFalseDeps.cpp | 41 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
288 RegClassInfo.runOnMachineFunction(mf, /*Rev=*/true); in runOnMachineFunction()
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| H A D | RegAllocEvictionAdvisor.cpp | 186 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
290 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterferenceBasedOnCost()
291 RegClassInfo.getNumAllocatableRegs( in canEvictInterferenceBasedOnCost()
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| H A D | RegAllocBase.cpp | 67 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
226 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(&RC); in getErrorAssignment()
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| H A D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocBase.h | 72 RegisterClassInfo RegClassInfo; variable
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| H A D | AllocationOrder.h | 85 const RegisterClassInfo &RegClassInfo,
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| H A D | RegAllocGreedy.cpp | 455 (2 * RegClassInfo.getNumAllocatableRegs(&RC))); in getPriority()
598 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
657 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
673 uint8_t MinCost = RegClassInfo.getMinCost(RC); in getOrderLimit()
683 OrderLimit = RegClassInfo.getLastCostChange(RC); in getOrderLimit()
700 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in canAllocatePhysReg()
1069 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1433 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1557 if (!RegClassInfo.isProperSubClass(CurRC)) { in tryInstructionSplit()
1578 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
[all …]
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| H A D | PostRASchedulerList.cpp | 83 RegisterClassInfo RegClassInfo; member in __anonf33d7a280111::PostRAScheduler
294 RegClassInfo.runOnMachineFunction(MF); in run()
298 SchedulePostRATDList Scheduler(MF, *MLI, AA, RegClassInfo, AntiDepMode, in run()
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| H A D | RegAllocFast.cpp | 190 RegisterClassInfo RegClassInfo; member in __anon43a0a7eb0111::RegAllocFastImpl
957 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
1008 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
1203 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in getErrorAssignment()
1411 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in findAndSortDefOperandIndexes()
1412 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in findAndSortDefOperandIndexes()
1841 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | AggressiveAntiDepBreaker.h | 123 const RegisterClassInfo &RegClassInfo; variable
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| H A D | MachineCombiner.cpp | 76 RegisterClassInfo RegClassInfo; member in __anon20cc5c180111::MachineCombiner
574 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo); in combineInstructions()
733 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | RegAllocPriorityAdvisor.cpp | 215 RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes), in RegAllocPriorityAdvisor()
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| H A D | CriticalAntiDepBreaker.cpp | 44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
398 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | RegAllocBasic.cpp | 265 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| H A D | MachineScheduler.cpp | 310 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
314 delete RegClassInfo; in ~MachineSchedContext()
571 RegClassInfo->runOnMachineFunction(*MF); in run()
1503 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1505 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1557 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1590 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1781 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
3716 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
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| H A D | AggressiveAntiDepBreaker.cpp | 123 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
613 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| H A D | RegAllocGreedy.h | 146 const RegisterClassInfo &getRegClassInfo() const { return RegClassInfo; } in getRegClassInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 45 RegisterClassInfo RegClassInfo; member in __anonf07969e70111::SIPreAllocateWWMRegs
109 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
207 RegClassInfo.runOnMachineFunction(MF); in run()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 241 struct RegClassInfo { struct
264 const RegClassInfo *const RCInfos; argument
273 const RegClassInfo *const RCIs,
847 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| H A D | MachineScheduler.h | 151 RegisterClassInfo *RegClassInfo; member
408 RegisterClassInfo *RegClassInfo;
448 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| H A D | RegAllocPriorityAdvisor.h | 45 const RegisterClassInfo &RegClassInfo; variable
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| H A D | MachinePipeliner.h | 77 RegisterClassInfo RegClassInfo; variable
287 const RegisterClassInfo &RegClassInfo; variable
379 RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI), in SwingSchedulerDAG()
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| H A D | RegAllocEvictionAdvisor.h | 145 const RegisterClassInfo &RegClassInfo; variable
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| H A D | VLIWMachineScheduler.h | 80 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
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