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Searched refs:RegClassID (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp115 unsigned RegClassID; in Select() local
122 RegClassID = R600::R600_Reg64RegClassID; in Select()
126 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
128 RegClassID = R600::R600_Reg128RegClassID; in Select()
133 SelectBuildVector(N, RegClassID); in Select()
H A DAMDGPUISelDAGToDAG.h93 void SelectBuildVector(SDNode *N, unsigned RegClassID);
H A DAMDGPUISelDAGToDAG.cpp441 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
446 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
463 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
564 unsigned RegClassID = in Select() local
566 SelectBuildVector(N, RegClassID); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h545 unsigned getUndefInitOpcode(unsigned RegClassID) const override { in getUndefInitOpcode() argument
546 if (RegClassID == ARM::MQPRRegClass.getID()) in getUndefInitOpcode()
548 if (RegClassID == ARM::SPRRegClass.getID()) in getUndefInitOpcode()
550 if (RegClassID == ARM::DPR_VFP2RegClass.getID()) in getUndefInitOpcode()
552 if (RegClassID == ARM::GPRRegClass.getID()) in getUndefInitOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h122 const char* getRegClassName(unsigned RegClassID) const;
125 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
H A DAMDGPUDisassembler.cpp169 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
1159 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
1161 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1180 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
1182 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
1184 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h289 unsigned getUndefInitOpcode(unsigned RegClassID) const override { in getUndefInitOpcode() argument
290 switch (RegClassID) { in getUndefInitOpcode()
H A DRISCVISelDAGToDAG.cpp251 unsigned RegClassID; in createTuple() local
263 RegClassID = M1TupleRegClassIDs[NF - 2]; in createTuple()
269 RegClassID = M2TupleRegClassIDs[NF - 2]; in createTuple()
275 RegClassID = RISCV::VRN2M4RegClassID; in createTuple()
282 Ops.push_back(CurDAG.getTargetConstant(RegClassID, DL, MVT::i32)); in createTuple()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1115 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1176 bool parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo);
1641 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1643 switch (RegClassID) { in GetSIDIForRegClass()
1677 int RegClassID = -1; in VerifyAndAdjustOperands() local
1698 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1699 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1705 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1707 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1709 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp517 unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass; in scavengeRegister()
518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local
H A DAArch64RegisterInfo.td708 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
943 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
984 # RegClass # "RegClassID>";
1041 # RegClass # "RegClassID>";
1149 # RegClassSuffix # "RegClassID>";
1190 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1586 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1727 # EltSize # ", AArch64::" # RC # "RegClassID>";
1754 # EltSize # ", AArch64::" # RC # "RegClassID>";
1789 # EltSize # ", AArch64::" # RC # "RegClassID>";
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp41 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
330 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
338 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg); in DecodeSimpleRegisterClass()
1576 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1583 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h2271 virtual unsigned getUndefInitOpcode(unsigned RegClassID) const { in getUndefInitOpcode() argument
2272 (void)RegClassID; in getUndefInitOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp77 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { in isMemOperand() argument
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1305 unsigned RegClassID; in convertVRToVRMx() local
1307 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1309 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1311 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1315 &RISCVMCRegisterClasses[RegClassID]); in convertVRToVRMx()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1403 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1405 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1408 template <unsigned RegClassID, int ExtWidth>
1413 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1874 template<unsigned Bits, unsigned RegClassID>
1877 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()