Searched refs:RegBytes (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1862 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister() local
1863 if (RegBytes > 8) in canHardenRegister()
1867 unsigned RegIdx = Log2_32(RegBytes); in canHardenRegister()
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| H A D | X86InstrInfo.h | 51 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
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| H A D | X86InstrInfo.cpp | 3403 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand, in getCMovOpcode() argument
3405 switch (RegBytes) { in getCMovOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9821 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad() local
9822 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; in expandUnalignedLoad()
9834 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedLoad()
9835 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedLoad()
9849 Offset += RegBytes; in expandUnalignedLoad()
9972 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore() local
9973 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; in expandUnalignedStore()
9986 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedStore()
9987 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedStore()
10003 Offset += RegBytes; in expandUnalignedStore()
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