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Searched refs:Reg64 (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp234 const Register Reg64 = MI->getOperand(0).getReg(); in expandLoadStackGuard() local
235 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard()
243 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
246 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64) in expandLoadStackGuard()
247 .addReg(Reg64) in expandLoadStackGuard()
257 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0); in expandLoadStackGuard()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1874 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad() local
1876 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1880 ResultReg = Reg64; in emitLoad()
4026 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext() local
4028 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
4032 ResultReg = Reg64; in emiti1Ext()
4551 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad() local
4553 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4557 Reg = Reg64; in optimizeIntExtLoad()
H A DAArch64RegisterInfo.td648 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
656 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
685 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
691 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
697 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
703 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
H A DAArch64InstrInfo.cpp10050 Register Reg64 = TRI.getSubReg(Reg, AArch64::dsub); in buildClearRegister() local
10051 BuildMI(MBB, Iter, DL, get(AArch64::FMOVD0), Reg64); in buildClearRegister()