Home
last modified time | relevance | path

Searched refs:Reg64 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp232 const Register Reg64 = MI->getOperand(0).getReg(); in expandLoadStackGuard() local
233 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard()
241 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
244 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64) in expandLoadStackGuard()
245 .addReg(Reg64) in expandLoadStackGuard()
255 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0); in expandLoadStackGuard()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1878 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad() local
1880 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1884 ResultReg = Reg64; in emitLoad()
4028 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext() local
4030 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
4034 ResultReg = Reg64; in emiti1Ext()
4548 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad() local
4550 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4554 Reg = Reg64; in optimizeIntExtLoad()
H A DAArch64RegisterInfo.td600 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
608 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
626 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
632 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
638 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
644 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {